CN-122003130-A - Semiconductor device including bonding pad and method of measuring contact resistance of bonding pad

Abstract

The present application relates to a semiconductor device including a bond pad and a method of measuring contact resistance of the bond pad. A semiconductor device includes a first test pattern in which a first upper test pad, a first upper test contact, and a first upper conductive layer connected to the first upper test contact are sequentially connected, a second test pattern in which a second lower test pad, a second lower test contact, and a second lower conductive layer connected to the second lower test contact are sequentially connected, and a third test pattern including a third upper conductive layer, a third lower conductive layer, a third upper test contact, a third upper test pad, a third lower test pad, and a third lower test contact.

Inventors

• ZHANG XIANLONG

Assignees

• 爱思开海力士有限公司

Dates

Publication Date

20260508

Application Date

20251015

Priority Date

20241101

Claims (18)

1. 1. A semiconductor device, comprising: A memory chip including a unit bonding pad disposed in a unit region and an upper test pad disposed outside the unit region, the upper test pad including a first upper test pad, a second upper test pad, and a third upper test pad; A circuit chip including peripheral bonding pads disposed in the unit region and lower test pads disposed outside the unit region, the lower test pads including a first lower test pad, a second lower test pad, and a third lower test pad, and Test patterns disposed outside the cell regions, each of the test patterns including at least a portion of the upper test pad or the lower test pad, Wherein the peripheral bond pad is bonded to the unit bond pad, and Wherein the test pattern includes: A first test pattern in which the first upper test pads, first upper test contacts, and first upper conductive layers are sequentially connected, the first upper test contacts being connected to each of the first upper test pads, the first upper conductive layers being connected to the first upper test contacts connected to different ones of the first upper test pads; A second test pattern in which the second lower test pads, second lower test contacts, and second lower conductive layers are sequentially connected, the second lower test contacts being connected to each of the second lower test pads, the second lower conductive layers being connected to the second lower test contacts connected to different ones of the second lower test pads, and A third test pattern including a third upper conductive layer, a third lower conductive layer, a third upper test contact connected to the third upper conductive layer, the third upper test pad connected to the third upper test contact, the third lower test pad connected to the third upper test pad, and a third lower test contact connected to the third lower test pad and the third lower conductive layer.
2. 2. The semiconductor device of claim 1, further comprising a pair of probing pads, each of the probing pads being connected to the first, second, or third test patterns, Wherein the probing pad includes a first probing input pad and a first probing output pad connected to the first test pattern at different positions, a second probing input pad and a second probing output pad connected to the second test pattern at different positions, and a third probing input pad and a third probing output pad connected to the third test pattern at different positions, Wherein voltages of different magnitudes are applied to the first probing input pad and the first probing output pad, the second probing input pad and the second probing output pad, or the third probing input pad and the third probing output pad, respectively, Wherein the resistance between the first probing input pad and the first probing output pad, between the second probing input pad and the second probing output pad, or between the third probing input pad and the third probing output pad is measured based on a value of a current flowing between the first probing input pad and the first probing output pad, between the second probing input pad and the second probing output pad, or between the third probing input pad and the third probing output pad.
3. 3. The semiconductor device of claim 2, wherein voltages of different magnitudes are applied to the first probing input pad and the first probing output pad connected to the first test pattern, and a first resistance between the first upper test pad and the first upper test contact is measured based on a value of a current flowing between the first probing input pad and the first probing output pad, Wherein voltages of different magnitudes are applied to the second probing input pad and the second probing output pad connected to the second test pattern, and a second resistance between the second lower test pad and the second lower test contact is measured based on a value of a current flowing between the second probing input pad and the second probing output pad, Wherein voltages of different magnitudes are applied to the third probe input pad and the third probe output pad connected to the third test pattern, and a third resistance between the third upper test contact and the third lower test contact is measured based on a value of a current flowing between the third probe input pad and the third probe output pad, and Wherein a contact resistance between the cell bond pad and the peripheral bond pad is measured by subtracting the first resistance and the second resistance from the third resistance.
4. 4. The semiconductor device of claim 1, wherein the first test pattern further comprises the first lower test pad bonded to each of the first upper test pads.
5. 5. The semiconductor device of claim 1, wherein the second test pattern further comprises the second upper test pad bonded to each of the second lower test pads.
6. 6. The semiconductor device of claim 1, wherein the third upper test pad included in the third test pattern overlaps with two or more of the third lower test pads.
7. 7. The semiconductor device of claim 6, wherein voltages of different magnitudes are applied to the second probing input pad and the second probing output pad connected to the second test pattern, and a second resistance between the second lower test pad and the second lower test contact is measured based on a value of a current flowing between the second probing input pad and the second probing output pad; Wherein voltages of different magnitudes are applied to the third probing input pad and the third probing output pad connected to the third test pattern, and a fourth resistance between the third upper test pad and the third lower test contact is measured based on a value of a current flowing between the third probing input pad and the third probing output pad, and Wherein a contact resistance between the cell bond pad and the peripheral bond pad is measured by subtracting the second resistance from the fourth resistance.
8. 8. The semiconductor device of claim 1, wherein the first through third upper test pads are disposed on the same layer as the unit bond pads.
9. 9. The semiconductor device according to claim 1, wherein the memory chip further comprises a peripheral region surrounding the cell region, and wherein the first test pattern, the second test pattern, and the third test pattern are disposed in the peripheral region.
10. 10. The semiconductor device according to claim 1, wherein the memory chip further comprises a chip region including the cell region and a peripheral region surrounding the cell region, and wherein the first test pattern, the second test pattern, and the third test pattern are disposed in a scribe line region continuous with the chip region.
11. 11. A semiconductor device, comprising: a memory chip including a unit bonding pad disposed in a unit region, and an upper test pad disposed outside the unit region; A circuit chip including peripheral bonding pads disposed in the unit region and bonded to the unit bonding pads, and lower test pads disposed outside the unit region, and A test pattern disposed outside the cell region and including at least a portion of the upper test pad or the lower test pad, Wherein at least one of the test patterns includes a portion of the upper test pads and a portion of the lower test pads, Wherein the upper test pad of each of the portions is bonded to the lower test pads of both of the portions, and the lower test pad of each of the portions is bonded to the upper test pads of both of the portions.
12. 12. The semiconductor device of claim 11, further comprising a pair of probe pads connected to at least one of the test patterns, Wherein the probing pad includes a probing input pad and a probing output pad connected to at least one of the test patterns at different positions, Wherein voltages of different magnitudes are applied to the probing input pad and the probing output pad, and measuring a resistance between the probing input pad and the probing output pad based on a value of a current flowing between the probing input pad and the probing output pad.
13. 13. The semiconductor device of claim 12, wherein voltages of different magnitudes are applied to the probing input pad and the probing output pad connected to at least one of the test patterns, and the contact resistance between the upper test pad and the lower test pad is measured by measuring the resistance between the probing input pad and the probing output pad based on a value of a current flowing between the probing input pad and the probing output pad.
14. 14. The semiconductor device according to claim 11, wherein the memory chip further comprises a peripheral region surrounding the cell region, and wherein at least one test pattern is disposed in the peripheral region.
15. 15. A method of measuring contact resistance for determining bond strength between a unit bond pad and a peripheral bond pad bonded to each other using at least a portion of upper test pads including a first upper test pad, a second upper test pad, and a third upper test pad or lower test pads including a first lower test pad, a second lower test pad, and a third lower test pad, the method comprising: Measuring a first resistance between the first upper test pad and a first upper test contact connected to the first upper test pad; Measuring a second resistance between the second lower test pad and a second lower test contact connected to the second lower test pad; Measuring a third resistance between a third upper test contact and a third lower test contact in a test pattern in which the third upper test contact, the third upper test pad, the third lower test pad, and the third lower test contact are sequentially connected, and Measuring a contact resistance between the unit bond pad and the peripheral bond pad by subtracting the first resistance and the second resistance from the third resistance, and evaluating the bonding strength between the unit bond pad and the peripheral bond pad based on the contact resistance.
16. 16. The method of claim 15, wherein measuring the first resistance comprises: Connecting a pair of probing pads to a first test pattern in which the first upper test pads, the first upper test contacts, and a first upper conductive layer connecting the first upper test contacts are connected in sequence, each of the first upper test contacts being connected to a different first upper test pad, and Different voltages are applied to the pair of probe pads, respectively.
17. 17. The method of claim 15, wherein measuring the second resistance comprises: Connecting a pair of probing pads to a second test pattern in which the second lower test pads, the second lower test contacts, and a second lower conductive layer connecting the second lower test contacts are connected in sequence, each of the second lower test contacts being connected to a different second lower test pad, and Different voltages are applied to the pair of probe pads, respectively.
18. 18. The method of claim 15, wherein one of the third upper test pads overlaps at least two of the third lower test pads when measuring the third resistance.

Description

Semiconductor device including bonding pad and method of measuring contact resistance of bonding pad Cross Reference to Related Applications The present application claims priority from korean patent application No. 10-2024-0153570 filed on 1 month 11 of 2024, which is incorporated herein by reference in its entirety. Technical Field Embodiments of the present disclosure relate generally to semiconductor technology, and more particularly, to a semiconductor device including a bond pad and a method of measuring a contact resistance of the bond pad. Background Memory devices are an important component in the electronics industry due to their characteristics of miniaturization, versatility, and/or low manufacturing cost. With the development of the electronic industry, the integration level of memory devices is also gradually improved. In order to achieve high integration of memory devices, a technology has been proposed in which various semiconductor device components and circuits are fabricated on two separate wafers, and then the two wafers are bonded together in a vertical direction using a wafer bonding technology. This technology is relatively new and requires further improvement. Disclosure of Invention Various embodiments of the present disclosure provide a semiconductor device including bonding pads and a method of measuring contact resistance of the bonding pads, which can accurately measure resistance between the bonding pads. Various embodiments of the present disclosure provide a semiconductor device including a memory chip including a unit bonding pad disposed in a unit region, and an upper test pad disposed outside the unit region, the upper test pad including a first upper test pad, a second upper test pad, and a third upper test pad, a circuit chip including a peripheral bonding pad disposed in the unit region and bonded to the unit bonding pad, and a lower test pad disposed outside the unit region, the lower test pad including a first lower test pad, a second lower test pad, and a third lower test pad, and test patterns disposed outside the unit region, each test pattern including at least a portion of the upper test pad and the lower test pad. In this case, the test pattern may include a first test pattern in which a first upper test pad, a first upper test contact connected to each first upper test pad, and a first upper conductive layer connected to the first upper test contact connected to a different first upper test pad are sequentially connected, a second test pattern in which a second lower test pad, a second lower test contact connected to each second lower test pad, and a second lower conductive layer connected to the second lower test contact connected to a different second lower test pad are sequentially connected, and a third test pattern including a third upper conductive layer, a third lower conductive layer, a third upper test contact connecting the third upper conductive layer with the third lower conductive layer, a third upper test pad, a third lower test pad, and a third lower test contact. Various embodiments of the present disclosure may provide a semiconductor device including a memory chip including a unit bonding pad disposed in a unit region and an upper test pad disposed outside the unit region, a circuit chip including a peripheral bonding pad disposed in the unit region and bonded to the unit bonding pad and a lower test pad disposed outside the unit region, and a test pattern disposed outside the unit region including at least a portion of the upper test pad and the lower test pad. At least one of the test patterns may include a portion of the upper test pads and a portion of the lower test pads. Each of the partial upper test pads may be bonded to two of the partial lower test pads, and each of the partial lower test pads may be bonded to two of the partial upper test pads. Various embodiments of the present disclosure may provide a method of measuring contact resistance for determining bonding strength between a cell bonding pad and a peripheral bonding pad bonded to each other using at least a portion of an upper test pad (including a first upper test pad, a second upper test pad, and a third upper test pad) and a lower test pad (including a first lower test pad, a second lower test pad, and a third lower test pad). The method may include measuring a first resistance between a first upper test pad and a first upper test contact connected to the first upper test pad, measuring a second resistance between a second lower test pad and a second lower test contact connected to the second lower test pad, measuring a third resistance between a third upper test contact and a third lower test contact in a test pattern in which the third upper test contact, the third upper test pad, the third lower test pad, and the third lower test contact are sequentially connected, measuring a contact resistance between the unit bonding pad and the peripheral bonding pad by subtractin