CN-122003135-A - Mini LED test method, system and computer

CN122003135ACN 122003135 ACN122003135 ACN 122003135ACN-122003135-A

Abstract

The invention relates to the technical field of semiconductors and provides a Mini LED test method, a system and a computer, wherein the method comprises the steps of obtaining a wafer outer ring threshold value, a first forward voltage interval and a second forward voltage interval; the wafer is tested through the probe set to obtain a plurality of voltage test data and a plurality of grain coordinates, a plurality of first retest grains are selected based on a wafer outer ring threshold and the plurality of grain coordinates, a plurality of second retest grains are selected from the plurality of first retest grains based on a first forward voltage interval and the plurality of voltage test data, a reference probe is determined from the plurality of probes to test the plurality of second retest grains to obtain a plurality of voltage retest data, and wafer yield is obtained based on the plurality of voltage retest data and the second forward voltage interval. By adopting the method, the probe bias or abnormal grain spacing is automatically processed, the false yield is corrected in time, and the material waste is avoided.

Inventors

ZHU BINGBING
GUO LEI
XU ZHOU
WEN GUOSHENG
Jin Conglong

Assignees

江西耀驰科技有限公司
江西兆驰半导体有限公司

Dates

Publication Date: 20260508
Application Date: 20260210

Claims (10)

1. The Mini LED testing method is characterized by comprising the following steps of: acquiring a wafer outer ring threshold value, a first forward voltage interval and a second forward voltage interval; testing a wafer by a probe set to obtain a plurality of voltage test data and a plurality of die coordinates of a plurality of dies in the wafer, wherein the probe set comprises a plurality of probes; selecting a plurality of first retest grains from a plurality of grains based on the wafer outer ring threshold and a plurality of grain coordinates; selecting a plurality of second retest grains from a plurality of first retest grains based on the first forward voltage interval and a plurality of voltage test data; Determining a reference probe from a plurality of probes according to the number of probes of the probe group and the probe arrangement rule, and testing a plurality of second retested grains through the reference probe to obtain a plurality of voltage retested data; And obtaining the wafer yield based on the voltage retest data and the second forward voltage interval.
2. The Mini LED testing method of claim 1, further comprising, prior to said step of selecting a first retest die from a plurality of said dies based on said wafer outer ring threshold and a plurality of said die coordinates: establishing a plurality of voltage test data located in the first forward voltage interval as a plurality of NG test data; Based on a plurality of NG test data and all the voltage test data, calculating the NG rate; And acquiring an NG rate threshold, and judging whether to send out an alarm signal based on the NG rate threshold and the NG rate.
3. The Mini LED testing method of claim 1, wherein said selecting a first plurality of retested dies from a plurality of said dies based on said wafer outer ring threshold and a plurality of said die coordinates comprises: Determining a wafer outer ring region based on the wafer outer ring threshold; And judging whether the crystal grain is positioned in the outer ring area of the wafer based on the crystal grain coordinates, and if the crystal grain is not positioned in the outer ring area of the wafer, determining the crystal grain as a first retest crystal grain.
4. The Mini LED testing method according to claim 2, wherein the step of selecting a number of second retest dies from the number of first retest dies comprises: and establishing a plurality of first retest grains corresponding to the plurality of NG test data as a plurality of second retest grains.
5. The Mini LED testing method of claim 4, wherein the minimum voltage value of the first forward voltage interval is greater than the maximum voltage value of the second forward voltage interval, further comprising, after the step of selecting a number of the first retest dies corresponding to a number of the NG test data as a number of the second retest dies: Establishing a plurality of voltage test data which are positioned outside the first forward voltage interval and the second forward voltage interval as a plurality of test data to be judged; Establishing a plurality of to-be-judged test data smaller than the minimum voltage value of the second forward voltage interval as a plurality of abnormal test data, and establishing a plurality of to-be-judged test data larger than the minimum voltage value of the second forward voltage interval as a plurality of selected test data, wherein the plurality of selected test data correspond to a plurality of selected grains; Acquiring a plurality of optical test data and a plurality of optical test thresholds of a plurality of selected dies, and establishing a plurality of second re-tested dies from the plurality of selected dies based on the plurality of optical test data and the plurality of optical test thresholds.
6. The Mini LED testing method of claim 1, wherein the plurality of probes correspond to a plurality of test channels, and after the step of selecting a plurality of second re-test dies from the plurality of first re-test dies based on the first forward voltage interval and the plurality of voltage test data, further comprising: dividing the plurality of second re-measured grains into a plurality of channel grain groups based on the plurality of test channels; Obtaining a channel threshold, and comparing the number of crystal grains in the channel crystal grain groups with the channel threshold to select a plurality of crystal grain groups to be inspected from a plurality of channel crystal grain groups; and checking a plurality of probes corresponding to the plurality of crystal grain groups to be checked through a CCD (charge coupled device) to judge whether probe deflection occurs, and sending out an alarm signal if the probe deflection occurs.
7. The Mini LED testing method according to claim 1, wherein the step of testing the plurality of second re-tested dies by the reference probe specifically comprises: And acquiring the hardware coordinates of the second re-measured crystal grain, and moving the probe group based on the hardware coordinates to enable the reference probe to be aligned with the second re-measured crystal grain for testing.
8. The Mini LED testing method according to claim 2, further comprising, prior to the step of obtaining a wafer yield based on the plurality of voltage retest data and the second forward voltage interval: Based on a plurality of voltage retest data and all the voltage test data, retest NG rate is calculated; And judging whether to retest again or not based on the NG rate threshold and the retest NG rate.
9. A Mini LED test system applying the Mini LED test method according to any one of the preceding claims 1-8, characterized in that the system comprises: the acquisition module is used for acquiring a wafer outer ring threshold value, a first forward voltage interval and a second forward voltage interval; The testing module is used for testing the wafer through a probe set to obtain a plurality of voltage testing data and a plurality of grain coordinates of a plurality of grains in the wafer, wherein the probe set comprises a plurality of probes; a first selecting module, configured to select a number of first retest grains from a number of grains based on the wafer outer ring threshold and a number of the grain coordinates; The second selecting module is used for selecting a plurality of second retest grains from a plurality of first retest grains based on the first forward voltage interval and a plurality of voltage test data; The retest module is used for determining a reference probe from a plurality of probes according to the number of probes of the probe set and the probe arrangement rule, and testing a plurality of second retest grains through the reference probe so as to obtain a plurality of voltage retest data; and the yield module is used for obtaining the wafer yield based on the voltage retest data and the second forward voltage interval.
10. A computer comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the Mini LED test method according to any one of claims 1 to 8 when executing the computer program.

Description

Mini LED test method, system and computer Technical Field The invention relates to the technical field of semiconductors, in particular to a Mini LED test method, a system and a computer. Background The processing of the wafer needs to undergo the processes of surface mounting, scribing, splitting, film turning, testing and the like. The wafer patch is to attach the whole wafer on a white film to provide a stable support, ensure the accurate alignment in the subsequent automatic production process, scribe the wafer by a wafer laser cutting technology, the picosecond or femtosecond laser beam with high repetition frequency penetrates through the surface of the wafer and focuses on the set depth inside the substrate, the nonlinear absorption effect of the wafer patch can form a continuous and homogeneous internal modified layer in a focal area, the structure of the internal modified layer is changed and the strength is obviously reduced, the front and the back of the wafer are kept intact, the splitting thoroughly separates the chip array still in a connected state into independent single pieces, the film turning is to transfer the whole wafer still adhered on the original cut white film to a special blue film which is easy to pick up the chip, and the test is to obtain the basic electrical characteristic data of the chip through a probe. However, in the film turning process, the arrangement pitch of the crystal grains is easy to deviate, and due to abnormal arrangement of the pitch, in the multi-channel synchronous test, the position where part or a single channel probe contacts the crystal grains deviates, so that effective electric connection cannot be formed, and abnormal test data is caused, the system misjudges the crystal grains with the probe being pricked as bad crystal grains, so that the calculated wafer yield is low, false defective products are easy to appear, and the perfect crystal grains are judged as defective products to be scrapped, so that a great amount of raw material loss exists. In the prior art, the phenomenon of probe deflection or data abnormality can be alarmed, but the alarm belongs to post-alarming, the automatic processing of abnormal grain spacing is lacked, the alarm is not timely responded by manual intervention, when the condition of probe deflection occurs, the dynamic adjustment of a test task is lacked, all grains in charge of a channel with an offset probe have the phenomenon of being mistested and missed test, and invalid batched test data are obtained. Disclosure of Invention Aiming at the defects of the prior art, the invention aims to provide a Mini LED test method, a system and a computer, according to the invention, the crystal grains needing to be retested are actively screened, and retested is carried out by adopting the reference probe, so that the dynamic adjustment of the test task after alarming is realized, and the defect is actively compensated. The invention aims to solve the technical problems that the prior art lacks automatic treatment of probe bias or abnormal grain spacing and is difficult to correct false yield in time. In order to achieve the above object, the present invention is achieved by the following technical scheme: a Mini LED test method comprises the following steps: acquiring a wafer outer ring threshold value, a first forward voltage interval and a second forward voltage interval; testing a wafer by a probe set to obtain a plurality of voltage test data and a plurality of die coordinates of a plurality of dies in the wafer, wherein the probe set comprises a plurality of probes; selecting a plurality of first retest grains from a plurality of grains based on the wafer outer ring threshold and a plurality of grain coordinates; selecting a plurality of second retest grains from a plurality of first retest grains based on the first forward voltage interval and a plurality of voltage test data; Determining a reference probe from a plurality of probes according to the number of probes of the probe group and the probe arrangement rule, and testing a plurality of second retested grains through the reference probe to obtain a plurality of voltage retested data; And obtaining the wafer yield based on the voltage retest data and the second forward voltage interval. Further, before the step of selecting a number of first retest dies from a number of the dies based on the wafer outer ring threshold and the number of die coordinates, the method further comprises: establishing a plurality of voltage test data located in the first forward voltage interval as a plurality of NG test data; Based on a plurality of NG test data and all the voltage test data, calculating the NG rate; And acquiring an NG rate threshold, and judging whether to send out an alarm signal based on the NG rate threshold and the NG rate. Still further, the step of selecting a number of first retest dies from a number of the dies based on the wafer outer ring threshold and a number of