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CN-122003136-A - Test method, device, equipment, medium and system for test structure on wafer

CN122003136ACN 122003136 ACN122003136 ACN 122003136ACN-122003136-A

Abstract

The application provides a testing method, a testing device, testing equipment, testing media and testing systems for testing structures on wafers, and relates to the technical field of semiconductor testing. The method comprises the steps of obtaining a test structure coordinate file of a wafer to be tested, wherein the test structure coordinate file comprises identification characters and identification positions of a plurality of test structures on the wafer to be tested, the identification positions are positions of the identification characters on the corresponding test structures, obtaining detection images of the plurality of test structures by adopting image acquisition equipment according to the identification positions of the plurality of test structures, and testing the test structures according to the detection images of the test structures. According to the application, a test automation flow frame is built, high-precision detection of the coordinates of the test structure is realized while manual intervention and detection time consumption are reduced, the problems of kneeling needle, wafer scratch, abnormal test data and the like caused by coordinate deviation are avoided, and the wafer shipment yield is ensured.

Inventors

  • LI FUHUI
  • WU YONGJIAN

Assignees

  • 广州增芯科技有限公司

Dates

Publication Date
20260508
Application Date
20260212

Claims (10)

  1. 1. A method for testing a test structure on a wafer, comprising: The method comprises the steps of obtaining a test structure coordinate file of a wafer to be tested, wherein the test structure coordinate file comprises identification characters of a plurality of test structures on the wafer to be tested and identification positions, and the identification positions are positions of the identification characters on the corresponding test structures; acquiring detection images of a plurality of test structures by adopting image acquisition equipment according to the identification positions of the plurality of test structures; and testing the test structure according to the detection image of the test structure.
  2. 2. The method of claim 1, wherein the acquiring, with the image capturing device, the detection images of the plurality of test structures according to the identified positions of the plurality of test structures, comprises: Controlling the image acquisition equipment to move to the identification position of the first test structure according to the identification position of the first test structure in the plurality of test structures so as to acquire a detection image of the first test structure; and sequentially controlling the image acquisition equipment to move to the identification positions of other test structures so as to sequentially acquire detection images of the other test structures.
  3. 3. The method of claim 1, wherein each test structure comprises a plurality of test keys, the identified location being a location of a first test key of the identified character on the corresponding test structure; The method for acquiring the detection images of the test structures by using the image acquisition equipment according to the identification positions of the test structures comprises the following steps: And acquiring an image of a first test key on each test structure by adopting the image acquisition equipment according to the identification position of each test structure as a detection image of each test structure.
  4. 4. A method according to claim 3, wherein said testing the test structure from the detected image of the test structure comprises: Performing frame recognition on the image of the first test key to determine a detection frame of the first test key; and testing the test structure according to the detection frame of the first test key.
  5. 5. The method of claim 4, wherein the testing the test structure according to the detection frame of the first test key comprises: Performing character recognition on the image of the first test key to obtain a detection position of the identification character on the corresponding test structure; determining an expected frame of the first test key according to the detection position of the identification character; Determining whether each edge in the detection frame and the expected frame of the first test key meets a preset deviation condition; If all the edges meet the preset deviation condition, determining that the test structure passes detection; And if at least one side does not meet the preset deviation condition, determining that the test structure test is not passed.
  6. 6. The method of claim 5, wherein before determining whether each of the detected and expected edges of the first test key meets a preset deviation condition, the method further comprises: and determining the preset deviation condition and the shooting range of the image acquisition equipment according to the size of the bonding pad corresponding to the test key.
  7. 7. A test apparatus for testing a structure on a wafer, comprising: The device comprises an acquisition module, a test structure coordinate file and a test module, wherein the acquisition module is used for acquiring the test structure coordinate file of a wafer to be tested, and the test structure coordinate file comprises identification characters and identification positions of a plurality of test structures on the wafer to be tested, wherein the identification positions are positions of the identification characters on the corresponding test structures; The acquisition module is used for acquiring detection images of a plurality of test structures by adopting image acquisition equipment according to the identification positions of the plurality of test structures; And the test module is used for testing the test structure according to the detection image of the test structure.
  8. 8. A control device, comprising a processor, a storage medium and a bus, wherein the storage medium stores program instructions executable by the processor, the processor and the storage medium communicate via the bus when the control device is running, and the processor executes the program instructions to implement the method for testing a test structure on a wafer according to any one of claims 1 to 6.
  9. 9. A readable storage medium having stored thereon program instructions which, when executed by a processor, implement the method of testing a test structure on a wafer of any of claims 1 to 6.
  10. 10. The test system is characterized by comprising a control device, a probe machine, a test machine and an image acquisition device; the probe machine table, the testing machine table and the image acquisition equipment are respectively connected with the control equipment; The control apparatus is configured to execute the test method of the test structure on a wafer according to any one of claims 1 to 6.

Description

Test method, device, equipment, medium and system for test structure on wafer Technical Field The present application relates to the field of semiconductor testing technology, and in particular, to a testing method, apparatus, device, medium and system for testing structures on a wafer. Background In the semiconductor manufacturing process, the electrical performance Test of the wafer is a Key link for guaranteeing the product quality and the shipment yield, wherein a Test Key (TSK) is used as a core needle insertion part of an electrical Test needle card, and the reliability of a Test result is directly determined by the coordinate accuracy of the Test structure. TSK is usually laid out in the dicing groove of the wafer, avoids the effective chip area, does not influence the normal function of the chip, and can realize the comprehensive monitoring of the wafer manufacturing process. After the process etching procedure is completed, PIE (process integration engineer) or TDPIE (research and development process integration engineer) provides TSK coordinate data for the WAT machine (wafer acceptance test machine) to identify and execute the test procedure. However, due to the manual intervention in the coordinate transfer process, deviations between the given TSK coordinates and the actual TSK coordinates on the wafer are very likely to occur. When the deviation exceeds a reasonable range, a series of irreversible adverse effects, such as physical damages of kneeling needles, scratching wafers shot and the like, are easily caused when the needle card is inserted, the wafer defect rate is directly increased, the wafer shipment yield is seriously affected, meanwhile, the coordinate deviation or different TSK coordinate disorders can also cause abnormal test data, the WAT machine test report error is caused, and the judgment of the wafer process stability is interfered. To solve the above problem, the WAT engineer (wafer test engineer) must check the TSK coordinates one by one when performing the probe tool program setup. Currently, the mainstream calibration mode in the industry is manual inspection, WAT engineers manually input coordinates one by one on the probe machine equipment, and judge the matching degree of the actual position of the TSK and the input coordinates through naked eyes. However, with the development of semiconductor technology, the number of TSKs on a single wafer is greatly increased, the manual inspection efficiency is only about 200 pieces/hour, and for wafers with a large number of TSKs, the mode needs to consume a large amount of working time of WAT engineering, so that the overall efficiency of a test flow is obviously reduced, meanwhile, the subjectivity and fatigue of manual operation further increase the error risk of coordinate correction, the accuracy of TSK coordinates cannot be fundamentally ensured, and the large-scale production and yield improvement of semiconductor manufacturing are restricted. Disclosure of Invention The present application is directed to the above-mentioned shortcomings in the prior art, and provides a testing method, device, equipment, medium and system for testing a structure on a wafer, so as to solve the problems in the prior art. The technical scheme adopted by the embodiment of the application is as follows: In a first aspect, an embodiment of the present application provides a method for testing a test structure on a wafer, including: The method comprises the steps of obtaining a test structure coordinate file of a wafer to be tested, wherein the test structure coordinate file comprises identification characters of a plurality of test structures on the wafer to be tested and identification positions, and the identification positions are positions of the identification characters on the corresponding test structures; acquiring detection images of a plurality of test structures by adopting image acquisition equipment according to the identification positions of the plurality of test structures; and testing the test structure according to the detection image of the test structure. In an embodiment, the acquiring, by using an image acquisition device, detection images of a plurality of test structures according to the identification positions of the plurality of test structures includes: Controlling the image acquisition equipment to move to the identification position of the first test structure according to the identification position of the first test structure in the plurality of test structures so as to acquire a detection image of the first test structure; and sequentially controlling the image acquisition equipment to move to the identification positions of other test structures so as to sequentially acquire detection images of the other test structures. In an embodiment, each test structure includes a plurality of test keys, and the identification position is a position of a first test key of the identification character on the corresponding tes