CN-122003137-A - Method for testing defect of semiconductor device and semiconductor device

CN122003137ACN 122003137 ACN122003137 ACN 122003137ACN-122003137-A

Abstract

The embodiment of the application discloses a defect testing method of a semiconductor device and the semiconductor device, wherein the method comprises the steps of testing a first test value of an off-state drain current of a transistor in the semiconductor device; the method comprises the steps of applying hot carrier injection stress to a transistor in a semiconductor device to excite transient electronic defects of an inner liner layer in a shallow trench isolation structure, testing a second test value of off-state drain current of the transistor in the semiconductor device, and judging whether the inner liner layer has the electronic defects or not by comparing the change conditions of the off-state drain current before and after the hot carrier injection stress is applied. The embodiment of the application realizes the rapid, efficient and sensitive detection of the instantaneous electronic defects of the lining layer in the shallow trench isolation structure.

Inventors

DONG LIN
WANG ZHONGSHENG
MAO CHENCHEN
JIANG PAN

Assignees

合肥晶合集成电路股份有限公司

Dates

Publication Date: 20260508
Application Date: 20260409

Claims (10)

1. A defect testing method of a semiconductor device including a shallow trench isolation structure having an inner liner layer, the defect testing method comprising: testing a first test value of an off-state drain current of a transistor in the semiconductor device; Applying hot carrier injection stress to transistors in the semiconductor device to excite transient electronic defects of the liner layer in the shallow trench isolation structure; testing a second test value of an off-state drain current of a transistor in the semiconductor device; and judging whether the inner liner has electronic defects or not by comparing the change conditions of the off-state drain current before and after the hot carrier injection stress is applied.
2. The defect testing method of claim 1, wherein the applying hot carrier injection stress to the transistors in the semiconductor device comprises: and applying a specific bias voltage to the gate and the drain of the transistor in the semiconductor device to enable the transistor to work in a saturation region.
3. The defect testing method of claim 2, wherein the specific bias voltage is set to a voltage interval that maximizes the number of electron-hole pairs generated.
4. The defect testing method of claim 1, wherein the determining whether the liner has an electronic defect by comparing the change of the off-state drain current before and after the application of the hot carrier injection stress comprises: Calculating the difference or the change multiple of the first test value and the second test value, if the difference or the change multiple exceeds a preset threshold value, judging that the inner liner has electronic defects, And if the difference value or the change multiple does not exceed the preset threshold value, judging that the inner liner has no electronic defect.
5. The defect testing method of claim 1, wherein prior to the testing the first test value of the off-state drain current of the transistor in the semiconductor device, the defect testing method further comprises: Preparing a dedicated test structure on a semiconductor wafer, the test structure comprising one or more types of transistors; Transistors belonging to the same type are respectively connected in parallel in a test structure to form one or more parallel transistor arrays so as to be convenient for respectively measuring the off-state drain current change before and after the hot carrier injection stress is applied to each parallel transistor array.
6. The defect testing method of claim 5, wherein the one or more types of transistors have the same channel width but different channel lengths, or the one or more types of transistors have different channel widths but the same channel lengths.
7. The defect testing method of claim 6, wherein the separately measuring the off-state drain current variation before and after the application of hot carrier injection stress to each parallel transistor array comprises: testing a first test value of an off-state drain current of each parallel transistor array for the parallel transistor array; applying hot carrier injection stress to the parallel transistor array to excite transient electronic defects of the liner layer in the shallow trench isolation structure; A second test value of an off-state drain current of the parallel transistor array is tested.
8. The defect testing method of claim 7, wherein the determining whether the liner has an electronic defect by comparing the change in the off-state drain current before and after the application of the hot carrier injection stress comprises: calculating a difference or a multiple of change between the first test value and the second test value for each parallel transistor array respectively in the case that the channel widths of the one or more types of transistors are the same and the channel lengths are different; if the difference or the multiple of change increases with the decrease of the channel length of the parallel transistor array, it is determined that the inner liner of the transistor of the semiconductor device has an electronic defect.
9. The defect testing method of claim 7, wherein the determining whether the liner has an electronic defect by comparing the change in the off-state drain current before and after the application of the hot carrier injection stress comprises: calculating a difference or a multiple of change between the first test value and the second test value for each parallel transistor array respectively in the case that the channel widths of the one or more types of transistors are different and the channel lengths are the same; if the difference or the multiple of change increases with the decrease of the channel width of the parallel transistor array, it is determined that the inner liner of the transistor of the semiconductor device has an electron defect.
10. A semiconductor device to which an inner liner of a shallow trench isolation structure is subjected to a defect test according to the defect test method of any one of claims 1 to 9.

Description

Method for testing defect of semiconductor device and semiconductor device Technical Field The present application relates to the field of semiconductor manufacturing technology, and in particular, to a defect testing method for a semiconductor device and a semiconductor device. Background In advanced semiconductor manufacturing processes, shallow Trench Isolation (STI) techniques are widely used to achieve electrical isolation between adjacent active regions. To suppress loss of active region silicon and improve device performance, a thin liner layer, often a silicon nitride (SiN) material called "liner SiN", is deposited on the STI trench sidewalls and bottom. However, during PMOS transistor operation, electrons are easily energized enough to form hot electrons under the action of a high electric field and are trapped by the liner layer on top of the STI structure, thereby forming transient electron defects such as electron traps at the interface or in the body. These electron defects may cause hot electron induced punch-through (HEIP) resulting in an abnormal increase in leakage current of the transistor in the off state. This problem is particularly pronounced after high temperature operating lifetime testing (High Temperature Operating Life Test, HTOL), manifesting as threshold voltage drift and rising standby current (also known as off-state drain current), severely affecting the long-term reliability of the device. Currently, HTOL testing is primarily relied upon to evaluate the impact of such electronic defects on device reliability. However, the conventional HTOL test has many limitations that firstly, the test period is up to about 1000 hours, the packaging time is required to be additionally considered, the process development progress is seriously dragged, secondly, once failure occurs, the electronic defect position is required to be positioned through means such as complicated Electrical Fault Analysis (EFA), and the like, the process is complicated, the cost is high, furthermore, devices with different channel width-to-length ratios (W/L) are affected by the HEIP to different degrees, and small-size devices are more sensitive, so that the failure mechanism is difficult to trace. Disclosure of Invention In view of the above problems, the present application aims to provide a defect testing method for a semiconductor device and a semiconductor device, which are aimed at overcoming the technical bottlenecks of long testing period, difficult positioning and low efficiency of the conventional HTOL, and realizing rapid, efficient and sensitive detection of instantaneous electronic defects of an inner liner layer in a Shallow Trench Isolation (STI) structure. According to a first aspect of an embodiment of the present application, there is provided a defect testing method of a semiconductor device, the semiconductor device including a shallow trench isolation structure having an inner liner layer, the defect testing method including: testing a first test value of an off-state drain current of a transistor in the semiconductor device; Applying hot carrier injection stress to transistors in the semiconductor device to excite transient electronic defects of the liner layer in the shallow trench isolation structure; testing a second test value of an off-state drain current of a transistor in the semiconductor device; and judging whether the inner liner has electronic defects or not by comparing the change conditions of the off-state drain current before and after the hot carrier injection stress is applied. Optionally, the applying hot carrier injection stress to the transistor in the semiconductor device includes: and applying a specific bias voltage to the gate and the drain of the transistor in the semiconductor device to enable the transistor to work in a saturation region. Optionally, the specific bias voltage is set to a voltage interval that maximizes the number of electron-hole pairs generated. Optionally, the determining whether the liner layer has an electronic defect by comparing the change condition of the off-state drain current before and after the application of the hot carrier injection stress includes: Calculating the difference or the change multiple of the first test value and the second test value, if the difference or the change multiple exceeds a preset threshold value, judging that the inner liner has electronic defects, And if the difference value or the change multiple does not exceed the preset threshold value, judging that the inner liner has no electronic defect. Optionally, before the testing the first test value of the off-state drain current of the transistor in the semiconductor device, the defect testing method further includes: Preparing a dedicated test structure on a semiconductor wafer, the test structure comprising one or more types of transistors; Transistors belonging to the same type are respectively connected in parallel in a test structure to form one or more p