CN-122003140-A - Semiconductor structure forming method and semiconductor structure

CN122003140ACN 122003140 ACN122003140 ACN 122003140ACN-122003140-A

Abstract

A method of forming a semiconductor structure includes etching at least one conductive structure to form an opening separating the conductive structure into shorter portions, and applying at least one passivation process to the portions above the opening. The method may also include forming a layer of non-conformal material having a lower fixed charge concentration than silicon nitride. In some embodiments, the non-conformal material layer has a first portion over the opening passivated by at least one passivation process, and the non-conformal material layer has a second portion extending to the base of the opening, the first portion of the non-conformal material layer having a thickness that is less than the second portion of the non-conformal material layer. In some embodiments, the method further comprises depositing a fill dielectric over the non-conformal material layer.

Inventors

FANG JIAYU
Ke Zhongting
Shi Bozheng
LI ZILIANG

Assignees

台湾积体电路制造股份有限公司

Dates

Publication Date: 20260508
Application Date: 20260113
Priority Date: 20250114

Claims (10)

1. A method of forming a semiconductor structure, comprising: etching at least one conductive structure to form an opening separating the conductive structure into shorter portions; Applying at least one passivation treatment to an upper portion of the opening; Forming a non-conformal material layer having a first fixed charge concentration, wherein the non-conformal material layer has a first portion passivated by the at least one passivation process on the upper portion of the opening, and the non-conformal material layer has a second portion extending to a base of the opening, the first portion of the non-conformal material layer having a thickness less than the second portion of the non-conformal material layer, and A fill dielectric is deposited over the non-conformal material layer, the fill dielectric having a second fixed charge concentration that is higher than the first fixed charge concentration.
2. The method of claim 1, wherein the at least one conductive structure comprises a plurality of semiconductor regions.
3. The method of claim 1, wherein the at least one conductive structure comprises a gate structure over a semiconductor region.
4. The method of claim 1, wherein the non-conformal material layer comprises silicon oxide, silicon oxynitride, or silicon oxycarbonitride.
5. The method of claim 1, wherein the passivation process is a heat process comprising a temperature above 600 ̊ C in an inert gas atmosphere comprising hydrogen, helium, nitrogen, or a combination thereof, wherein the heat process comprises a pressure of 10 torr to 5 atmospheres.
6. The method of claim 1, wherein the passivation process is a plasma process comprising a plasma comprising argon, helium, hydrogen, or a combination thereof, wherein the plasma process comprises a temperature of 300 ̊ C to 500 ̊ C, wherein the plasma process comprises a pressure of 10 torr to 5 atmospheres.
7. The method of claim 1, wherein a thickness difference between the first portion of the non-conformal material layer and the second portion of the non-conformal material layer is 2 nm to 10 nm.
8. A method of forming a semiconductor structure, comprising: etching at least one conductive structure to form an opening separating the conductive structure into shorter portions; Forming a buffer layer having a fixed charge concentration lower than that of silicon nitride; Etching the buffer layer to produce a non-conformal thickness, wherein the non-conformal thickness of the buffer layer comprises a first portion in an upper portion of the opening, the first portion having a thickness less than a second portion of the buffer layer in a base portion of the opening, and A fill dielectric is deposited over the buffer layer having the non-conformal thickness.
9. The method of claim 8, further comprising forming a low-k dielectric fill over the fill dielectric, wherein the fill dielectric comprises silicon nitride.
10. A semiconductor structure, comprising: At least one conductive feature; a trench extending through the conductive feature, and A trench fill comprising: A non-conformal material layer having a first fixed charge concentration, wherein the non-conformal material layer has a first portion on an upper portion of the trench, the first portion having a first thickness, and the non-conformal material layer has a second portion extending through a base of the trench and having a second thickness, wherein the second thickness is less than the first thickness, and A fill dielectric has a second fixed charge concentration that is higher than the first fixed charge concentration on the non-conformal material layer.

Description

Semiconductor structure forming method and semiconductor structure Technical Field The present disclosure relates to a semiconductor structure forming method and a semiconductor structure. Background Advances in Integrated Circuit (IC) materials and design techniques have resulted in one generation of yet another, with each generation of integrated circuits having smaller and more complex circuitry than the previous generation. During the development of integrated circuits, the functional density (e.g., the number of interconnected elements per unit wafer area) has increased as a whole and the geometry has decreased. This scaling down process can generally provide benefits by increasing production efficiency and reducing associated costs. This scaling down also increases the complexity of the integrated circuit process and fabrication, and similar developments are required in the process and fabrication of integrated circuits to achieve these advances. For example, dielectrics (e.g., dielectric materials) may be used as spacers, liners, and gap fill materials for the purpose of element isolation. However, in some cases, the dielectric material may have a high level of positive fixed charge due to point defects. In some cases, high levels of positive fixed charges within semiconductor devices can lead to various device performance problems. Disclosure of Invention According to one embodiment of the present disclosure, a method of forming a semiconductor structure includes etching at least one conductive structure to form an opening separating the conductive structure into shorter portions, applying a passivation process to the upper portions of the opening, forming a layer of non-conformal material having a first fixed charge concentration over the upper portions of the opening, wherein the layer of non-conformal material has a first portion passivated by the passivation process and the layer of non-conformal material has a second portion extending to a base of the opening, the first portion of the layer of non-conformal material has a thickness less than the second portion of the layer of non-conformal material, and depositing a fill dielectric over the layer of non-conformal material, the fill dielectric having a second fixed charge concentration that is higher than the first fixed charge concentration. According to one embodiment of the present disclosure, a method of forming a semiconductor structure includes etching at least one conductive structure to form an opening separating the conductive structure into shorter portions, forming a buffer layer having a lower fixed charge concentration than silicon nitride, etching the buffer layer to create a non-conformal thickness, wherein the non-conformal thickness of the buffer layer includes a first portion in an upper portion of the opening having a thickness that is less than a second portion of the buffer layer in a base portion of the opening, and depositing a fill dielectric over the buffer layer having the non-conformal thickness. According to one embodiment of the present disclosure, a semiconductor structure includes at least one conductive feature, a trench, and a trench fill. The trench extends through the conductive feature. The trench fill includes a layer of non-conformal material and a fill dielectric. The non-conformal material layer has a first fixed charge concentration, wherein the non-conformal material layer has a first location on an upper portion of the trench, the first location having a first thickness, and the non-conformal material layer has a second location extending through a base of the trench and having a second thickness, wherein the second thickness is less than the first thickness. The fill dielectric has a second fixed charge concentration that is higher than the first fixed charge concentration on the non-conformal material layer. Drawings The disclosure will be best understood from the following description when read in conjunction with the accompanying drawings. It is emphasized that, in accordance with the standard practice of the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Fig. 1 to 4, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 10C, 11 are views illustrating an intermediate stage in transistor formation according to some embodiments; Fig. 12A, 12B, 13A, 13B, 14A, 14B, 15A, 15B, 16A, 16B, 17A, 17B, 17C, 17D, 17E, 17F, 17G, 17H, 17I, 17J, 17K, 17L, 17M, 17N, 17O, and 17P are diagrams illustrating the formation of continuous polysilicon (continuous polysilicon on diffusion edge, CPODE) on the diffusion edge according to some embodiments; fig. 18A, 18B, 19A, 19B, 20 are views illustrating intermediate stages in transistor formation according to some embodiments; FIGS. 21-36 illustrate the formation of a Cut Metal Gate (CMG) isolation interface, in accord