CN-122003143-A - Preparation method of semiconductor structure and semiconductor structure

Abstract

The invention provides a preparation method of a semiconductor structure and the semiconductor structure, and relates to the technical field of semiconductors. The manufacturing method comprises the steps of providing a metal interconnection semi-finished product device, including a first dielectric layer, a metal layer arranged in and on the first dielectric layer, and a blocking layer for isolating the metal layer from the first dielectric layer, carrying out first planarization treatment on the metal layer by taking the blocking layer as a stop layer, forming a photosensitive dielectric layer on the surfaces of the blocking layer and the metal layer, carrying out second planarization treatment on the photosensitive dielectric layer by taking the blocking layer as the stop layer under a first illumination condition, carrying out third planarization treatment on the blocking layer under a dark condition, removing the blocking layer on the surface of the first dielectric layer, carrying out fourth planarization treatment on the residual photosensitive dielectric layer under a second illumination condition until the photosensitive dielectric layer is completely removed, and carrying out fifth planarization treatment on the residual metal layer. The preparation method can reduce notch recess in the junction area of the metal layer and the barrier layer, and is favorable for subsequent electrical stability.

Inventors

• LI WENQIN
• WANG WENXUAN

Assignees

• 合肥晶合集成电路股份有限公司

Dates

Publication Date

20260508

Application Date

20260410

Claims (10)

1. 1. A method of fabricating a semiconductor structure, comprising: Providing a metal interconnection semi-finished device, wherein the metal interconnection semi-finished device comprises a first dielectric layer, a metal layer arranged in and on the first dielectric layer, and a barrier layer for isolating the metal layer and the first dielectric layer; taking the barrier layer as a stop layer, and carrying out first planarization treatment on the metal layer; forming a photosensitive medium layer on the surfaces of the barrier layer and the metal layer; under the first illumination condition, carrying out second planarization treatment on the photosensitive medium layer by taking the blocking layer as a stop layer; under the light-shielding condition, carrying out third planarization treatment on the barrier layer, and removing the barrier layer on the surface of the first dielectric layer; under the second illumination condition, carrying out fourth planarization treatment on the rest photosensitive medium layer until the photosensitive medium layer is removed; And carrying out fifth planarization treatment on the rest metal layer.
2. 2. The method of claim 1, wherein forming a photosensitive dielectric layer on the barrier layer and the metal layer comprises: forming a second dielectric layer with holes distributed on the surfaces of the barrier layer and the metal layer; And grafting a photosensitive material in the holes.
3. 3. The preparation method of claim 2, wherein a plasma enhanced chemical vapor deposition process is adopted when forming a second dielectric layer on the surfaces of the barrier layer and the metal layer, an organosilicon precursor is selected as a precursor for forming the second dielectric layer, and the deposition temperature of the plasma enhanced chemical vapor deposition process is 200-250 ℃.
4. 4. The method of claim 2, wherein the photosensitive material comprises a ferrocene-anthraquinone complex.
5. 5. The method of claim 2, wherein after forming the second dielectric layer, the method further comprises a step of pre-treating the hole before the photosensitive material is received in the hole.
6. 6. The method of claim 2, wherein after forming the second dielectric layer, the method further comprises modifying the photosensitive material prior to receiving the photosensitive material within the hole.
7. 7. The method of claim 1, wherein the first illumination condition and the second illumination condition are selected from ultraviolet light.
8. 8. The method of claim 1, wherein the first planarization process, the second planarization process, the third planarization process, the fourth planarization process, and the fifth planarization process are all chemical mechanical polishing.
9. 9. The method according to claim 1, wherein the metal interconnect semi-finished device is cleaned after the first planarization process, the second planarization process, the third planarization process, the fourth planarization process, and the fifth planarization process, respectively.
10. 10. A semiconductor structure, characterized by being produced by the production method according to any one of claims 1 to 9.

Description

Preparation method of semiconductor structure and semiconductor structure Technical Field The present invention relates to the field of semiconductor technologies, and in particular, to a method for manufacturing a semiconductor structure and a semiconductor structure. Background In the semiconductor manufacturing process, the planarization process is a key link for realizing the preparation of the multilayer interconnection structure, wherein the planarization process for the metal interconnection layer is used as a key link of the preparation flow of the metal interconnection structure, and the electrical performance and the long-term reliability of the semiconductor interconnection structure are directly determined by the planarization precision. In the practical process implementation process, as the material characteristics of the metal interconnection layer and the substrate or the barrier layer and other structures are different, and the physical and chemical characteristics of the functional medium used in the process at the process interface are influenced, local concave defects are easily formed in the interface area between the metal interconnection layer and the adjacent structure, the defects are easy to cause slurry residues, and the defects can also cause poor filling of the subsequent medium layer to influence the integrity of the interconnection structure. The research shows that the metal material (such as copper) adopted for forming the metal layer of the metal interconnection structure generally has higher ductility, lower hardness and good chemical activity, and in the grinding process, on one hand, the metal material is easy to be extruded by mechanical grinding force to generate plastic deformation, and on the other hand, the metal material can generate more severe chemical corrosion reaction with functional media used for grinding to cause relatively higher removal rate of the metal material on the surface of the metal interconnection structure, while the barrier layer material is used as an isolation layer for blocking the diffusion function of metal atoms, and is generally made of a material with higher hardness and stronger chemical stability, the ductility of the barrier layer material is far lower than that of the metal material, and the chemical reaction activity of the barrier layer material with the functional media is weaker, so that the removal rate of the barrier layer material is obviously lower than that of the metal material on the surface of the metal interconnection structure under the same grinding process parameters. This uneven polishing removal rate may cause excessive metal material on the surface of the metal interconnection structure to be removed rapidly and simultaneously, the material on the surface of the barrier layer to be removed slowly during the polishing process, so that a step-like drop is formed in the interface area between the two, and the drop gradually evolves into a local notch recess (as shown by the structure in the red circle in fig. 1 and 2) along with the continuous progress of the polishing process. The invention patent CN108682650a discloses a surface planarization method and a semiconductor multilayer interconnection structure, which repair dishing generated in copper process by adopting polishing-deposition-polishing process. However, the technical scheme can only realize the post-repair of the defects, and cannot fundamentally solve the problem of notch recession of the junction area caused by the difference of the grinding rates between the metal layer and the barrier layer. Disclosure of Invention The invention provides a preparation method of a semiconductor structure and the semiconductor structure, which are used for reducing notch recess of a junction area between a metal layer and a barrier layer when a metal interconnection structure is formed. The invention provides a preparation method of a semiconductor structure, which comprises the following steps: Providing a metal interconnection semi-finished device, wherein the metal interconnection semi-finished device comprises a first dielectric layer, a metal layer arranged in and on the first dielectric layer, and a barrier layer for isolating the metal layer and the first dielectric layer; taking the barrier layer as a stop layer, and carrying out first planarization treatment on the metal layer; forming a photosensitive medium layer on the surfaces of the barrier layer and the metal layer; under the first illumination condition, carrying out second planarization treatment on the photosensitive medium layer by taking the blocking layer as a stop layer; under the light-shielding condition, carrying out third planarization treatment on the barrier layer, and removing the barrier layer on the surface of the first dielectric layer; under the second illumination condition, carrying out fourth planarization treatment on the rest photosensitive medium layer until the photosensitive med