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CN-122003149-A - PSUB packaging substrate based on single-sided substrate process and manufacturing method thereof

CN122003149ACN 122003149 ACN122003149 ACN 122003149ACN-122003149-A

Abstract

The embodiment of the application provides a PSUB packaging substrate based on a single-sided substrate process and a manufacturing method thereof, relating to the technical field of advanced packaging of semiconductors, comprising a metal substrate, wherein the upper surface of the metal substrate is covered with a high-heat-conductivity insulating film, the upper surface of the high-heat-conductivity insulating film is covered with a metallization seed layer, the upper surface of the metallization seed layer is covered with a plurality of layers of wiring structures, and each layer of wiring structure comprises a copper circuit, a conducting structure and an EMC filling layer. The application has the effect of combining high-density wiring and high current.

Inventors

  • HUANG GAO
  • HUAN XUN

Assignees

  • 苏州亿麦矽半导体技术有限公司

Dates

Publication Date
20260508
Application Date
20251210

Claims (6)

  1. 1. The PSUB packaging substrate manufacturing method based on the single-sided substrate process is characterized by comprising the following steps of: S1, coating or pressing a film on a metal substrate (1), and pressing a layer of high-heat-conductivity insulating film (2) on the metal substrate; s2, forming a metallization seed layer (3) on the high heat conduction insulating film (2) or the EMC filling layer (6) by adopting a magnetron sputtering or chemical copper mode; S3, forming a layer of copper circuit (4) and a layer of conducting structure (5) on the metallized seed layer (3) through continuous processes of exposing, developing and RDL electroplating of the photosensitive material twice, wherein the thickness of the copper circuit (4) is 5-50 mu m; S4, filling an EMC material into the wiring structure by adopting a plastic package film pressure process to form an EMC filling layer (6); s5, grinding the conducting structure (5) by adopting a grinding process; S6, repeating the steps S2-S5 for a plurality of times to form a multi-layer wiring structure, thereby realizing the manufacture of the PSUB substrate.
  2. 2. The method for manufacturing a PSUB package substrate based on a single-sided substrate process as claimed in claim 1, wherein the multi-layer wiring structure in the steps S3 to S5 is formed on a temporary carrier, the multi-layer wiring structure is bonded to the metal substrate (1) covered with the high thermal conductive insulating film (2) in the step S2 by a hot pressing process, and the temporary carrier is peeled off to complete the manufacture of the PSUB package substrate.
  3. 3. A method of manufacturing a PSUB package substrate based on a single-sided substrate process according to claim 1 or 2, further comprising the following packaging steps: s7, manufacturing copper columns (7) which are higher than the thickness of the chip to be packaged on the surface of the multilayer wiring structure of the PSUB substrate (12) manufactured in the step S6, wherein the height of each copper column (7) is 50-200 mu m; S8, attaching a bottom chip (8) with bumps between copper columns (7) on the surface of a PSUB substrate (12) in a positive mounting mode, wherein the bumps of the bottom chip (8) are electrically connected with a multilayer wiring structure of the PSUB substrate; S9, covering EMC materials on the surface of the PSUB substrate by adopting a plastic packaging film pressing process, embedding a bottom chip (8) and a copper column (7), and forming a packaging EMC layer (9); S10, grinding and packaging the EMC layer (9) by adopting a grinding process, so that a top connecting port of the bottom chip (8) is exposed; s11, attaching the upper chip (10) to the top connecting port of the exposed bottom chip (8) through a flip-chip process, and completing manufacturing of the packaging structure based on the PSUB substrate (12); If a multi-layer embedded chip structure is required to be fabricated in the step S9, the steps S7-S10 may be repeated, and EMC materials with different CTEs are used to solve the warpage problem, where the difference in thermal expansion coefficients of the EMC materials with different CTEs is controlled within 5×10 -6 /°c.
  4. 4. The PSUB packaging substrate based on the single-sided substrate process is characterized by comprising a metal substrate (1), wherein the upper surface of the metal substrate (1) is covered with a high-heat-conductivity insulating film (2), at least one layer of wiring structure is arranged on the high-heat-conductivity insulating film (2), each layer of wiring structure comprises a metallization seed layer (3), and a copper circuit (4), a conducting structure (5) and an EMC filling layer (6) are sequentially arranged on the metallization seed layer (3) from bottom to top.
  5. 5. A PSUB package substrate based on a single-sided substrate process as claimed in claim 4, wherein the metal substrate (1) is an aluminum plate or a copper plate.
  6. 6. The PSUB packaging substrate based on the single-sided substrate process of claim 4, further comprising a packaging structure, wherein the packaging structure comprises copper columns (7), a bottom chip (8), a packaging EMC layer (9) and an upper chip (10), the copper columns (7) are vertically fixed on the surface of a multi-layer wiring structure of the PSUB substrate (12), the height of the copper columns (7) is higher than the thickness of the bottom chip (8), the bottom chip (8) is embedded between the copper columns (7) in a positive mounting mode, protruding points of the bottom chip (8) are electrically connected with the multi-layer wiring structure of the PSUB substrate (12), the packaging EMC layer (9) covers the surface of the PSUB substrate (12) and wraps the copper columns (7) and the bottom chip (8), the top of the packaging layer (9) is exposed out of a top connection port of the bottom chip (8) after being ground, and the upper chip (10) is electrically connected with the top connection port of the bottom chip (8) through a flip chip process.

Description

PSUB packaging substrate based on single-sided substrate process and manufacturing method thereof Technical Field The invention relates to the technical field of advanced packaging of semiconductors, in particular to a PSUB packaging substrate based on a single-sided substrate process and a manufacturing method thereof. Background Along with the iteration of the semiconductor device to the high-density and high-power direction, the heat dissipation and signal interconnection of the electronic system become core bottlenecks, and the traditional electronic system package adopts a four-stage separation structure of a chip-SUB package carrier board-PCB circuit board-metal heat dissipation substrate, but the four-stage heat dissipation structure has low heat conductivity and cannot meet the heat dissipation requirement of the high-power device. The current PCB circuit board technology adopts an etching copper circuit technology, so that the wiring density of a chip grade cannot be realized, the SUB packaging carrier board adopts a semi-additive technology, high-density wiring can be realized, and the high-current requirement required by a passive element cannot be realized. In view of the foregoing, the inventors consider that there is a need for an integrated package substrate solution for high density routing and high current carrying. Disclosure of Invention In order to solve the problem that a carrier cannot achieve both high-density wiring and high-current bearing, the application provides a PSUB packaging substrate based on a single-sided substrate process and a manufacturing method thereof. The application provides a PSUB packaging substrate based on a single-sided substrate process and a manufacturing method thereof, which adopts the following technical scheme: a system integrated PSUB metal PCB packaging heat dissipation substrate manufacturing method based on a single-sided substrate process comprises the following steps: S1, coating or laminating a layer of high-heat-conductivity insulating film on a metal substrate by adopting a coating or laminating method; s2, forming a metallization seed layer on the high-heat-conductivity insulating film or the EMC filling layer by adopting a magnetron sputtering or chemical copper mode; s3, forming a layer of copper circuit and a layer of conducting structure on the metallized seed layer through continuous processes of exposing, developing and RDL electroplating of the photosensitive material twice, wherein the thickness of the copper circuit is 5-50 mu m; S4, filling an EMC material into the wiring structure by adopting a plastic package film pressure process to form an EMC filling layer; s5, grinding the conducting structure by adopting a grinding process; S6, repeating the steps S3-S5 for a plurality of times to form a multi-layer wiring structure, thereby realizing the manufacture of the PSUB substrate. Optionally, the multilayer wiring structure in the steps S2-S5 is fabricated on a temporary carrier, and the multilayer wiring structure is bonded to the metal substrate covered with the high-thermal-conductivity insulating film in the step S2 by a hot pressing process, and the PSUB substrate is fabricated after the temporary carrier is peeled off. Optionally, the method further comprises the following packaging steps: S7, manufacturing copper columns which are higher than the thickness of the chip to be packaged on the surface of the multilayer wiring structure of the PSUB substrate manufactured in the step S6, wherein the height of each copper column is 50-200 mu m; S8, attaching the bottom chip with the salient points between copper columns on the surface of the PSUB substrate in a forward mounting mode, wherein the salient points of the bottom chip are electrically connected with the multilayer wiring structure of the PSUB substrate; S9, covering EMC materials on the surface of the PSUB substrate by adopting a plastic packaging film pressing process, embedding a bottom chip and a copper column, and forming a packaging EMC layer; S10, grinding and packaging the EMC layer by adopting a grinding process, so that a top connecting port of a bottom chip is exposed; S11, attaching an upper chip to the top connecting port of the exposed bottom chip through a flip-chip process, and completing manufacturing of a packaging structure based on a PSUB substrate; If a multi-layer embedded chip structure is required to be fabricated in the step S9, the steps S7-S10 may be repeated, and EMC materials with different CTEs are used to solve the warpage problem, where the difference in thermal expansion coefficients of the EMC materials with different CTEs is controlled within 5×10 -6/°c. A PSUB packaging substrate based on a single-sided substrate process and a manufacturing method thereof comprise a metal substrate, wherein the upper surface of the metal substrate is covered with a high heat conduction insulating film, at least one layer of wiring structure is arranged on t