CN-122003151-A - Semiconductor package

Abstract

The application provides a semiconductor package. A semiconductor package may include a semiconductor die disposed on a first substrate and having at least a first contact on a first side and at least a second contact on a second side opposite the first side. An insulator (such as a dielectric material) may encapsulate the semiconductor die. The second substrate may be disposed on the first substrate with the semiconductor die between the first substrate and the second substrate. Either the first substrate or the second substrate may have cavities formed therein, and the semiconductor die may be disposed in one or both of the cavities. Vias through the first substrate, dielectric, and/or second substrate may be used to connect to the semiconductor die, thereby enabling formation of a redistribution layer. The magnetic element and associated windings may also be used in place of the semiconductor die and associated contacts.

Inventors

• Dinis Ramanathan
• Anders Soren Linde
• Vija B. Luntara
• Christopher Li Tesla
• Michael J. Seiden
• Gabriella Robert
• George. Ruble Guban

Assignees

• 半导体元件工业有限责任公司

Dates

Publication Date

20260508

Application Date

20251104

Priority Date

20251031

Claims (20)

1. 1. A semiconductor package, characterized in that, the semiconductor package includes: a substrate; A semiconductor die disposed on the substrate and having at least a first contact on a first side and at least a second contact on a second side opposite the first side; a dielectric encapsulant encapsulating the semiconductor die and having a via formed therein, and A redistribution layer formed on the dielectric sealing material and connected to the first contact and the second contact through the via.
2. 2. The semiconductor package of claim 1, further comprising a conductive layer electrically connected to the second contact and disposed between the second contact and the substrate, wherein the conductive layer is electrically connected to the redistribution layer through at least one of the vias.
3. 3. The semiconductor package of claim 1, wherein the semiconductor package further comprises a cavity formed in the substrate, wherein the semiconductor die is disposed within the cavity.
4. 4. The semiconductor package of claim 1, wherein the semiconductor package further comprises: and a second substrate formed of a semiconductor material and disposed on the dielectric sealing material, the second substrate having a second via formed therein, wherein the redistribution layer is formed on the second substrate and is connected to the first contact and the second contact through the via and the second via.
5. 5. The semiconductor package of claim 1, wherein the semiconductor package further comprises: a second semiconductor die disposed on the redistribution layer; A second dielectric encapsulation material formed over the redistribution layer and encapsulating the second semiconductor die, the second dielectric encapsulation material having a second via formed therein, and A second redistribution layer formed on the second dielectric encapsulation material, connected to the semiconductor die through the via and the second via, and connected to the second semiconductor die through the second via.
6. 6. The semiconductor package of claim 1, wherein the semiconductor package further comprises: a second substrate formed of a semiconductor material; A second semiconductor die disposed on a first side of the second substrate facing the semiconductor die; a second dielectric encapsulation material at least partially encapsulating the second semiconductor die; A second via formed through the second dielectric encapsulation material, wherein the semiconductor die and the second semiconductor die are connected by the second via; A third via formed through the second dielectric sealing material and through the second substrate; a fourth via formed through the second substrate, and A second redistribution layer formed at least in part on a second side of the second substrate opposite the first side of the second substrate and connected to the redistribution layer and the second semiconductor die through the second via, the third via, and the fourth via.
7. 7. The semiconductor package of claim 1, wherein the semiconductor package further comprises: A second substrate having a cavity formed therein, wherein the substrate is positioned within the cavity.
8. 8. A semiconductor package, characterized in that, the semiconductor package includes: a first substrate; A semiconductor die disposed on the first substrate; A second substrate having a cavity formed therein, the cavity defining a first portion of the second substrate having a first depth and a second portion of the second substrate having a second depth greater than the first depth, and the second substrate passing through the second portion of the second substrate and being attached to the first substrate with the semiconductor die disposed within the cavity; a through hole formed through the first portion of the second substrate, and And a contact portion disposed on the second substrate and electrically connected to the semiconductor die through the via.
9. 9. The semiconductor package of claim 8, wherein the via is a second via, the contact is a second contact, and the semiconductor package further comprises: A first via formed through the first substrate, and A first contact is disposed on the first substrate and electrically connected to the semiconductor die through the first via.
10. 10. The semiconductor package of claim 8, wherein the semiconductor package further comprises: a second via formed through the second portion of the second substrate; A metal layer formed between the semiconductor die and the first substrate and extending between the first substrate and the second portion of the second substrate, and A redistribution layer formed on the second substrate, the redistribution layer including the contact portion and a second contact portion electrically connected to the metal layer through the second via.
11. 11. The semiconductor package of claim 8, wherein the cavity is a second cavity, and the semiconductor package further comprises: A first cavity formed in the first substrate and aligned with the second cavity to form a combined cavity, wherein the semiconductor die is disposed within the combined cavity.
12. 12. The semiconductor package of claim 8, wherein the semiconductor package further comprises: A first metal attachment point between the first substrate and the second substrate; a second metal attachment point between the semiconductor die and the second substrate, and A third metal attachment point between the semiconductor die and the first substrate.
13. 13. The semiconductor package of claim 8, wherein the semiconductor package further comprises: A first metal layer extending through the first substrate and parallel to a surface of the semiconductor die and electrically connected to the semiconductor die; A second metal layer including the contact and extending through the second substrate and parallel to the surface of the semiconductor die; a second via formed through the second portion of the second substrate; A third through hole formed through the first substrate, and A redistribution layer formed on the first substrate between the first substrate and the second substrate, electrically connected to the first metal layer through the third via, and electrically connected to the second metal layer through the second via.
14. 14. The semiconductor package of claim 8, wherein the second substrate comprises a semiconductor substrate, and further comprising an electronic component formed in the second substrate and connected to the semiconductor die through the contact.
15. 15. The semiconductor package of claim 8, wherein at least one of the first and second substrates comprises a semiconductor substrate, and further comprising a microelectromechanical system element formed in at least one of the first and second substrates and connected to the semiconductor die through the contact.
16. 16. The semiconductor package of claim 15, wherein the semiconductor die and the microelectromechanical system element are combined to provide a relay.
17. 17. A semiconductor package, characterized in that, the semiconductor package includes: A substrate having a cavity formed therein; a magnetic element disposed in the cavity; A metal winding disposed on the substrate and surrounding the magnetic element; a dielectric sealing material sealing the magnetic element and the metal winding, and And a contact portion electrically connected to the metal winding through a via hole formed in the dielectric sealing material.
18. 18. The semiconductor package of claim 17, wherein the magnetic element comprises a cylindrical iron disk.
19. 19. The semiconductor package of claim 17, wherein the metal winding comprises a patterned metal layer coiled around the magnetic element in at least two turns.
20. 20. The semiconductor package of claim 17, wherein the metal winding has an inner terminal that is proximate to an edge of the magnetic element and that extends helically to an outer terminal that is distal from the magnetic element.

Description

Semiconductor package Cross Reference to Related Applications The application claims the benefits and priorities of U.S. provisional application No.63/715,912 filed on 4 at 11, 2024 and U.S. provisional application No.63/736,415 filed on 19 at 12, 2024, and U.S. non-provisional application 19/376,690 filed on 31, 2025, are incorporated herein by reference in their entirety. Technical Field The present description relates to semiconductor device packages. Background Conventional packaging techniques for semiconductor devices have a number of drawbacks. Such drawbacks are particularly problematic in the case of packaged semiconductor power devices, as such devices typically have multiple requirements that must be met simultaneously by the chosen packaging technology. For example, semiconductor power devices typically require high voltage and high temperature operation, requiring high voltage isolation for safety reasons, and high thermal conductivity to transfer heat to some type of heat sink. It is also generally desirable that power device packages be low cost and small in size, which further exacerbates the difficulty of meeting voltage/thermal requirements. In certain examples, it is desirable to provide a semiconductor module for a traction inverter of an electric vehicle that has low on-resistance across many parallel devices and low circuit parasitics, while maintaining the above-described requirements for low cost, small size, and voltage/thermal management. In another specific example, artificial intelligence (ARTIFICIAL INTELLIGENCE, AI) data centers have large-scale power requirements, but current packaging technology suffers from complexities such as those associated with multi-chip packaging within small package profiles (exacerbated by the use of flip-chip technology), poor thermal conductivity of the molding compound used for encapsulation, and undesirably large package volumes due to the inclusion of bond wires. Recent approaches have attempted to address the above and related challenges, such as approaches using printed circuit board (printed circuit board, PCB) embedding. However, these methods can be expensive and complex while still not satisfactorily solving the existing challenges. For example, PCB embedding typically requires expensive laser drilling for the through holes, while providing insufficient cooling. Disclosure of Invention According to one general aspect, a semiconductor package includes a substrate, a semiconductor die disposed on the substrate and having at least a first contact on a first side and at least a second contact on a second side opposite the first side, a dielectric encapsulation material encapsulating the semiconductor die and having a via formed therein, and a redistribution layer formed on the dielectric encapsulation material and connected to the first contact and the second contact through the via. According to another general aspect, a method of manufacturing a semiconductor package includes providing a semiconductor die on a substrate, the semiconductor die having at least a first contact on a first side and at least a second contact on a second side opposite the first side, sealing the semiconductor die with a dielectric encapsulation material, forming a via in the dielectric encapsulation material, and forming a redistribution layer on the dielectric encapsulation material, the redistribution layer being connected to the first contact and the second contact through the via. According to another general aspect, a semiconductor package includes a first substrate, a semiconductor die disposed on the first substrate, a second substrate having a cavity formed therein defining a first portion of the second substrate having a first depth and a second portion of the second substrate having a second depth greater than the first depth, and the second substrate is attached to the first substrate through the second portion of the second substrate and with the semiconductor die disposed within the cavity, a via formed through the first portion of the second substrate, and a contact disposed on the second substrate and electrically connected to the semiconductor die through the via. According to another general aspect, a method of manufacturing a semiconductor package includes disposing a semiconductor die on a first substrate, forming a cavity in a second substrate, the cavity defining a first portion of the second substrate having a first depth and a second portion of the second substrate having a second depth greater than the first depth, attaching the second substrate to the first substrate through the second portion of the second substrate and with the semiconductor die disposed within the cavity, forming a via through the first portion of the second substrate, and disposing a contact on the second substrate and electrically connecting the contact to the semiconductor die through the via. According to another general aspect, a semiconductor package includes a su