CN-122003153-A - Ceramic substrate power device package

CN122003153ACN 122003153 ACN122003153 ACN 122003153ACN-122003153-A

Abstract

The ceramic substrate power device package comprises a power transistor wafer, a drain electrode pad, a source electrode pad, a switch control electrode pad, a ceramic substrate, an insulating glue and a power transistor wafer, wherein the drain electrode pad is arranged on the bottom surface of the power transistor wafer, the source electrode pad and the switch control electrode pad are arranged on the top surface of the power transistor wafer, the ceramic substrate is used for bearing the wafer and comprises a top circuit layer and a ceramic substrate layer, the top circuit layer of the ceramic substrate is formed into an L-shaped top circuit layer through an etching process, the thickness of one side of the top circuit layer processed through the etching process is smaller, the power transistor wafer is welded on the top surface of the side of the L-shaped top circuit layer of the ceramic substrate, which is smaller in thickness, and the insulating glue is filled around the level of the power transistor wafer. The ceramic substrate is used as the drain electrode conductive sheet, the packaged drain electrode bonding pad, the radiating fin and the substrate of the power transistor wafer, and the radiating fin can be directly arranged on the circuit layer at the bottom layer of the ceramic substrate through the insulating property and the high thermal conductivity of the ceramic substrate layer, so that the radiating performance of the power device is improved.

Inventors

ZHAO ZHENTAO

Assignees

摩驱科技(深圳)有限公司

Dates

Publication Date: 20260508
Application Date: 20250420

Claims (4)

1. The ceramic substrate power device package is characterized by comprising a power transistor wafer, wherein a drain electrode pad is arranged on the bottom surface of the power transistor wafer, a source electrode pad and a switch control electrode pad are arranged on the top surface of the power transistor wafer, a ceramic substrate for bearing the wafer is further arranged, the ceramic substrate comprises a top layer circuit layer and a ceramic substrate layer, the top layer circuit layer of the ceramic substrate forms an L-shaped top layer circuit layer through an etching process, one side of the top layer circuit layer processed through the etching process is smaller in thickness, the power transistor wafer is welded on the top surface of the side of the ceramic substrate L-shaped top layer circuit layer through the drain electrode pad, a circuit board surface mounting process easily-welded metal layer is plated on the top surface of the side of the ceramic substrate L-shaped top layer circuit layer, the top surface of the power transistor wafer is flush with the top surface of the side of the ceramic substrate L-shaped top layer circuit layer, and the insulating filling glue is filled on the top surface of the side of the ceramic substrate L-shaped top layer circuit layer, and the periphery of the power transistor wafer is filled with the insulating filling glue.
2. The ceramic substrate power device package of claim 1 wherein the ceramic substrate comprises a top wiring layer, a ceramic substrate layer and a bottom wiring layer, wherein the top wiring layer of the ceramic substrate is etched to form an L-shaped top wiring layer.
3. The ceramic substrate power device package of claim 1, wherein the power transistor wafer is a diode wafer, an anode pad is arranged on the bottom surface of the diode wafer, a cathode pad is arranged on the top surface of the diode wafer, the diode wafer is welded on the top surface of the side, with smaller thickness, of the L-shaped top layer circuit layer of the ceramic substrate through the anode pad, and the top surface of the diode wafer is flush with the top surface of the side, with larger thickness, of the L-shaped top layer circuit layer of the ceramic substrate.
4. The ceramic substrate power device package of claim 1 wherein the power transistor wafer is a set of two or more transistor wafers bonded to the top surface of the lower thickness side of the L-shaped top wiring layer of the ceramic substrate through drain pads, respectively.

Description

Ceramic substrate power device package Technical Field The invention relates to a processing technology of a ceramic substrate, relates to a packaging technology of a power device, optimization of a chip heat dissipation technology and architecture design, and relates to packaging technologies of silicon-based transistors, third-generation and fourth-generation semiconductor transistors. Background The ceramic base circuit board is made up of ceramic base material and one or two conductive layers, and is made up by using copper foil directly bonded to the surface of ceramic base material at high temperature. Power transistors (e.g., MOSFETs, diodes, HEMTs, and IGBTs) are widely used in high power electronic devices such as power management modules, electric vehicle drive systems, and industrial motor control. The third generation semiconductor materials GaN (gallium nitride) and SiC (silicon carbide) are representatives of wide forbidden band semiconductors, and the power device manufactured by gallium nitride has the remarkable characteristics of high switching speed, low on-resistance, small chip area and the like, and is widely applicable to the fields of power adapters, industrial power supplies, automobile electronics and the like, and SiC transistors including diodes, MOS transistors and the like are widely used. Ultra-wideband power devices, which are mainly represented by diamond, gallium oxide and the like, are also coming into practical use. Conventional power transistor packages typically employ complex lead frame and metal clip structures to make electrical connection of the source, gate and drain. However, this packaging method has the problems of complicated process, large volume, limited heat dissipation performance, and influence on the device performance. Disclosure of Invention In order to solve the problems, the invention provides a power transistor packaging structure based on a ceramic substrate carrying a wafer, which not only simplifies the packaging process and improves the device performance, but also reduces the packaging volume by taking a wafer bonding pad as a packaging bonding pad, and improves the performance of a power device through the insulation performance and high thermal conductivity of the ceramic substrate layer. The power device package comprises a power transistor wafer, drain electrode pads are distributed on the bottom surface of the power transistor wafer, source electrode pads and switch control electrode pads are distributed on the top surface of the power transistor wafer, the pads distributed on the top surface and the bottom surface of the power transistor wafer adopt weldable materials in electronic product patch (SMT) production, nickel gold or nickel palladium gold is generally adopted, the power device package further comprises a ceramic substrate carrying the wafer, the ceramic substrate comprises a top layer circuit layer and a ceramic substrate layer, the top layer circuit layer of the ceramic substrate forms an L-shaped top layer circuit layer through an etching process, the top layer circuit layer is processed by the etching process, the power transistor wafer is welded on the top surface of the ceramic substrate L-shaped top layer circuit layer through the drain electrode pads, the top surface of the ceramic substrate L-shaped top layer circuit layer is plated with a circuit board surface mounting process easily welded metal layer, copper is generally plated or nickel gold, the top surface of the power transistor wafer is prevented from being oxidized, the top surface of the ceramic substrate L-shaped top layer is flush with the top surface of the ceramic substrate, the top layer is larger in thickness, the top layer is filled with the drain electrode pads, and the power transistor pads are filled on the periphery of the power transistor wafer, and the power transistor pads are filled on the top surface of the silicon wafer, and the drain electrode pads are filled on the top surface of the silicon wafer, and the silicon wafer is filled with the silicon wafer. In order to realize mass production, the ceramic substrate needs to be manufactured into a plurality of conjoined connecting plates of the ceramic substrate, and after the insulating glue is filled, the connecting plates are divided into individual small packages. Preferably, the ceramic substrate is a three-layer ceramic substrate, and comprises a top circuit layer, a ceramic substrate layer and a bottom circuit layer, wherein the top circuit layer of the ceramic substrate forms an L-shaped top circuit layer through an etching process. Preferably, the power transistor wafer is a diode wafer, an anode bonding pad is arranged on the bottom surface of the diode wafer, a cathode bonding pad is arranged on the top surface of the diode wafer, the diode wafer is welded on the top surface of the side, with smaller thickness, of the L-shaped top circuit layer of the ceramic substrate through the anode