CN-122003155-A - Chip interconnection structure, chip and preparation method of chip interconnection structure

Abstract

The application discloses a chip interconnection structure, a chip and a preparation method of the chip interconnection structure, wherein the chip interconnection structure comprises a first bare chip, a first chip and a second chip, wherein the first bare chip is provided with a first functional circuit and a first internal bus electrically connected with the first functional circuit, the first bare chip is provided with a first interconnection interface, and a signal wire of the first internal bus is directly connected to the first interconnection interface; the second die is provided with a second interconnection interface, signal lines of the second internal bus are directly connected to the second interconnection interface, and an interconnection interposer is used for electrically connecting the first interconnection interface and the second interconnection interface. The application can omit a special I/O circuit in the prior proposal, eliminate the delay and the power consumption introduced by the special I/O circuit and simplify the design proposal. In addition, the method can also support the separation of a large-size chip (integrated large-scale circuit) into a plurality of bare chips with miniaturized design, and reduce the overall design difficulty and period of the chip product.

Inventors

• ZHAO XUDONG

Assignees

• 北京华封集芯电子有限公司

Dates

Publication Date

20260508

Application Date

20251229

Claims (9)

1. 1. A chip interconnect structure, comprising: A first die having a first functional circuit and a first internal bus electrically connected to the first functional circuit, and provided with a first interconnection interface to which signal lines of the first internal bus are directly connected; A second die having a second functional circuit and a second internal bus electrically connected to the second functional circuit, and provided with a second interconnection interface to which signal lines of the second internal bus are directly connected, and And the interconnection interposer is arranged between the first die and the second die and is used for electrically connecting the first interconnection interface and the second interconnection interface so as to enable the first internal bus and the second internal bus to directly communicate.
2. 2. The chip interconnect structure of claim 1 wherein the first die and the second die are fabricated using different semiconductor process recipes.
3. 3. The chip interconnect structure of claim 1 or 2, wherein the first interconnect interface comprises a first array of micro-bumps and the second interconnect interface comprises a second array of micro-bumps, the number of micro-bumps in the first array of micro-bumps being the same as and in one-to-one correspondence with the number of micro-bumps in the second array of micro-bumps.
4. 4. The chip interconnect structure of claim 3 wherein the first array of micro bumps is formed at an edge region of a surface of the first die and the second array of micro bumps is formed at an edge region of a surface of the second die.
5. 5. The chip interconnect structure of claim 3, wherein the interconnect interposer is a silicon bridge having interconnect wires formed therein that connect the micro bumps in the first array of micro bumps to the micro bumps in the second array of micro bumps in a one-to-one correspondence.
6. 6. The chip interconnect structure of claim 1, further comprising at least one supplemental die having a third functional circuit and a third internal bus electrically connected to the third functional circuit, and the supplemental die being provided with a third interconnect interface to which signal lines of the third internal bus are directly connected; The interconnect interposer is further configured to electrically connect the third interconnect interface with the first interconnect interface and the second interconnect interface such that the third internal bus is in direct communication with the first internal bus and the second internal bus.
7. 7. The die interconnect structure of claim 6, wherein the supplemental die has a plurality of the supplemental dies each fabricated using a different semiconductor process.
8. 8. A chip comprising a package substrate, characterized in that the chip further comprises at least one chip interconnect structure according to any of claims 1 to 7, which is arranged on the package substrate.
9. 9. The preparation method of the chip interconnection structure is characterized by comprising the following steps of: Providing a first die having a first functional circuit and a first internal bus electrically connected to the first functional circuit and a second die having a second functional circuit and a second internal bus electrically connected to the second functional circuit; forming a first interconnect interface on the first die and a second interconnect interface on the second die; connecting the signal lines of the first internal bus directly to the first interconnect interface, and connecting the signal lines of the second internal bus directly to the second interconnect interface; An interconnection interposer is provided, with which the first interconnection interface is electrically connected to the second interconnection interface.

Description

Chip interconnection structure, chip and preparation method of chip interconnection structure Technical Field The application relates to the technical field of semiconductor packaging, in particular to a chip interconnection structure, a chip and a preparation method of the chip interconnection structure. Background With the rapid development of applications such as high-performance computing and artificial intelligence, more and more functional modules are integrated on a system-on-a-chip (SoC), which results in an increasing chip area. The large-size chip has high chip-flowing cost, and the product yield can be reduced along with the increase of the chip area, so that the production cost is obviously improved. For this purpose, a solution of a core particle (Chiplet) is proposed in the prior art, and the core particle (Chiplet) is a technical system for integrating the bare chips of different process nodes through advanced packaging technology to form a multifunctional modularized chip. The system on chip can be split into a plurality of bare chips, and the function multiplexing and the calculation force expansion are realized through heterogeneous combination, so that the design and manufacturing cost can be reduced, the research and development period can be shortened, and the manufacturing yield can be improved. The above solution requires interconnection of multiple dies, and to achieve high bandwidth, low latency communication between different dies, current solutions typically integrate dedicated high speed serial/deserializers (SerDes), physical layer interfaces (PHY, such as PCIe), or complex differential pair driver/receiver circuits in the I/O area of each die. The above interconnection scheme with the special I/O circuit structure has the problems of complex design, high cost and the like, and additionally increases delay and power consumption due to complex protocol conversion. Disclosure of Invention The present application aims to solve one of the technical problems in the related art to a certain extent. Therefore, the application provides a chip interconnection structure, a chip and a preparation method of the chip interconnection structure. In order to achieve the above purpose, the application adopts the following technical scheme that the chip interconnection structure comprises: A first die having a first functional circuit and a first internal bus electrically connected to the first functional circuit, and provided with a first interconnection interface to which signal lines of the first internal bus are directly connected; A second die having a second functional circuit and a second internal bus electrically connected to the second functional circuit, and provided with a second interconnection interface to which signal lines of the second internal bus are directly connected, and And the interconnection interposer is arranged between the first die and the second die and is used for electrically connecting the first interconnection interface and the second interconnection interface so as to enable the first internal bus and the second internal bus to directly communicate. The application has the advantages that the first internal bus in the first bare chip and the second internal bus in the second bare chip can realize direct communication by forming the first interconnection interface and the second interconnection interface on the first bare chip and the second bare chip respectively, directly connecting the first internal bus in the first bare chip to the first interconnection interface, directly connecting the second internal bus in the second bare chip to the second interconnection interface, and electrically connecting the first interconnection interface and the second interconnection interface by utilizing the interconnection interposer. Therefore, special I/O circuits such as a special high-speed serial/deserializer (SerDes), a physical layer interface (PHY (such as PCIe) or a complex differential pair driving/receiving circuit in the existing scheme can be omitted, the design scheme is simplified, and the manufacturing cost is reduced. Meanwhile, after the structural design is adopted, the signal transmission path does not need any protocol conversion or signal reshaping, and delay and power consumption introduced by a special I/O circuit are eliminated. In addition, inter-chip communication delay is mainly dependent on the physical length of the interconnect interposer, enabling near-chip communication performance. Furthermore, the application can also support the separation of a large-size chip (integrated large-scale circuit inside) into a plurality of bare chips which are convenient for miniaturization design, and the bare chips which are miniaturized design have the advantages of low design difficulty and short design period, can reduce the design difficulty of the whole chip product and the design period of the whole chip product, thereby reducing the manufacturing cost