CN-122003158-A - Semiconductor packaging structure and circuit assembly

CN122003158ACN 122003158 ACN122003158 ACN 122003158ACN-122003158-A

Abstract

The invention provides a semiconductor packaging structure and a circuit assembly. The semiconductor packaging structure comprises a substrate, a laminated structure arranged on one side of the substrate and used for adjusting the stress of the substrate, at least one cavity formed by the laminated structure, semiconductor devices arranged in the cavity and arranged at intervals, and the laminated structure comprises a first structure and a second structure which are arranged in a laminated mode, wherein the first structure is fixedly connected with the substrate, and the second structure is detachably connected with the first structure. The technical scheme provided by the embodiment solves the problems that the existing warpage control structure for the packaging structure of the large-size chip has poor warpage control effect and influences the packaging process and the heat dissipation effect of the packaging structure.

Inventors

CHEN GUIFANG
YIN PENGYUE
CHEN XIAOQIANG
LIU YANFEI
TIAN JIA
TANG YUE

Assignees

上海燧原科技股份有限公司

Dates

Publication Date: 20260508
Application Date: 20260204

Claims (12)

1. A semiconductor package structure, comprising: a substrate; the laminated structure is arranged on one side of the substrate and used for adjusting the stress of the substrate, and at least one cavity is formed by the laminated structure; the semiconductor device is arranged in the cavity and is arranged at intervals with the laminated structure; The laminated structure comprises a first structure and a second structure which are arranged in a laminated mode, wherein the first structure is fixedly connected with the substrate, and the second structure is detachably connected with the first structure.
2. The semiconductor package according to claim 1, wherein, The first structure is arranged between the substrate and the second structure; along the thickness direction of the substrate, the projection of the first structure at least partially overlaps the projection of the second structure.
3. The semiconductor package according to claim 1 or 2, wherein the semiconductor package further comprises: The first structure is fixedly connected with the substrate through the bonding layer, and/or, And the first structure and the second structure are detachably connected through the connecting structure.
4. The semiconductor package according to claim 3, wherein, The connection structure comprises temporary bonding glue and/or mechanical connectors.
5. The semiconductor package according to claim 1 or 2, wherein, The first structure comprises at least one layer of a first metal ring; the second structure comprises 1 metal cap and/or at least one layer of second metal ring.
6. The semiconductor package according to claim 5, wherein the stacked structure includes 1 of the metal cap and the at least one layer of the second metal ring: the metal cover is arranged on one side of the at least one layer of second metal ring away from the substrate, and/or, The metal cover at least partially covers the second metal ring in a thickness direction of the substrate, and/or, The projection of the metal cover at least partially covers the projection of the semiconductor device along the thickness direction of the substrate.
7. The semiconductor package according to claim 6, wherein, The stress of the laminated structure is regulated by the contact area between the first metal ring and the second metal ring, the contact area between two adjacent second metal rings and/or the contact area between the second metal ring and the metal cover; And/or the stress magnitude of the laminated structure is adjusted by the thermal expansion coefficients and/or the thickness of the first structure and the second structure.
8. The semiconductor package according to claim 5, wherein the material of the first metal ring and the second metal ring comprises metal; And/or the coefficient of thermal expansion of the first metal ring is different from the coefficient of thermal expansion of the second metal ring; and/or, in the case that the second structure includes at least two layers of second metal rings, the thermal expansion coefficients of the adjacent two layers of second metal rings are different; And/or, along the direction parallel to the substrate, the width of the metal ring is more than or equal to 1mm and less than or equal to 50mm; And/or the minimum distance between the semiconductor device and the laminated structure is more than or equal to 0.5mm and less than or equal to 50mm.
9. The semiconductor package according to claim 5, wherein, The thickness of the laminated structure is larger than that of the semiconductor device along the thickness direction of the substrate; And/or, the second structure of the laminated structure comprises a metal cover, and the semiconductor packaging structure further comprises a gasket, wherein the gasket is arranged between the semiconductor device and the metal cover.
10. A circuit assembly comprising the semiconductor package according to any one of claims 1 to 9.
11. The circuit assembly of claim 10, further comprising: A circuit board; The semiconductor packaging structure is arranged on at least one side of the circuit board, and the laminated structure of the semiconductor packaging structure is used for adjusting the stress of the substrate to be matched with the stress of the semiconductor packaging structure.
12. The circuit assembly according to claim 10 or 11, wherein, The second structure of the stacked structure of the semiconductor package is configured to be removed after the stress of the substrate of the semiconductor package matches the stress of the circuit board of the circuit assembly.

Description

Semiconductor packaging structure and circuit assembly Technical Field The embodiment of the invention relates to the technical field of semiconductors, in particular to a semiconductor packaging structure and a circuit assembly. Background As the heterostructure integration level of the chip is higher and higher, the power consumption and the packaging size of the chip are larger and larger. The chip and the substrate are attached to form a packaging structure, and the substrate has poor warpage. The size of the chip is increased, and the warpage of the substrate is also increased, which affects the yield of the whole package manufacturing process. And the mounting process challenges between the packaging structure and the PCB are also becoming larger and larger. The existing warpage control structure for the packaging structure of the large-size chip has the problems that the warpage control effect is poor, and the packaging process and the heat dissipation effect of the packaging structure are affected, so that the problem is a technical problem to be solved in the industry. Disclosure of Invention The embodiment of the invention provides a semiconductor packaging structure and a circuit assembly, which are used for solving the problems that the existing warping control structure of the packaging structure of a large-size chip has poor warping control effect and influences the packaging process and the heat dissipation effect of the packaging structure. In order to realize the technical problems, the invention adopts the following technical scheme: the embodiment of the invention provides a semiconductor packaging structure, which comprises the following components: a substrate; the laminated structure is arranged on one side of the substrate and is used for adjusting the stress of the substrate; The semiconductor device is arranged in the cavity and is arranged at intervals with the laminated structure; The laminated structure comprises a first structure and a second structure which are arranged in a laminated mode, the first structure is fixedly connected with the substrate, and the second structure is detachably connected with the first structure. Optionally, the first structure is disposed between the substrate and the second structure; Along the thickness direction of the substrate, the projection of the first structure at least partially overlaps the projection of the second structure. Optionally, the semiconductor package structure further includes: the first structure is fixedly connected with the substrate through the bonding layer, and/or, The first structure and the second structure are detachably connected through the connecting structure. Optionally, the connection structure comprises temporary bonding glue and/or mechanical connectors. Optionally, the first structure comprises at least one layer of a first metal ring; The second structure comprises 1 metal cap and/or at least one layer of second metal ring. Optionally, in the case that the laminated structure comprises 1 metal cap and at least one layer of second metal ring: the metal cover is arranged on one side of the at least one layer of second metal ring away from the substrate, and/or, The metal cover at least partially covers the second metal ring in the thickness direction of the substrate, and/or, The projection of the metal cap at least partially covers the projection of the semiconductor device in the thickness direction of the substrate. Optionally, the stress of the laminated structure is adjusted by the contact area between the first metal ring and the second metal ring, the contact area between two adjacent second metal rings, and/or the contact area between the second metal ring and the metal cover; And/or the stress level of the laminate structure is adjusted by the coefficient of thermal expansion and/or the thickness of the first structure and the second structure. Optionally, the material of the first metal ring and the second metal ring includes metal; And/or the coefficient of thermal expansion of the first metal ring is different from the coefficient of thermal expansion of the second metal ring; And/or, in the case that the second structure comprises at least two layers of second metal rings, the coefficients of thermal expansion of the adjacent two layers of second metal rings are different; And/or, along the direction parallel to the substrate, the width of the metal ring is more than or equal to 1mm and less than or equal to 50mm; And/or, the minimum distance between the semiconductor device and the laminated structure is more than or equal to 0.5mm and less than or equal to 50mm. Optionally, the thickness of the stacked structure is greater than the thickness of the semiconductor device along the thickness direction of the substrate; And/or the second structure of the laminated structure comprises a metal cover, and the semiconductor packaging structure further comprises a gasket, wherein the gasket is arranged