CN-122003159-A - Package substrate and semiconductor package including the same

Abstract

A package substrate includes a core having a first surface and a second surface opposite the first surface in a vertical direction, the first surface and the second surface being substantially flat, the core including glass and a first recess in the first surface, a first bonding layer contacting the first surface of the core and filling the first recess, a through electrode extending from the first surface through the core in the vertical direction, the through electrode being spaced apart from the first recess in a horizontal direction, a first wiring structure on the first bonding layer and contacting the through electrode, a first insulating layer structure on the first bonding layer and partially covering the first wiring structure, and a first protection layer on the first insulating layer structure and covering an upper surface of a portion of the first wiring structure.

Inventors

• Pu Yujing

Assignees

• 三星电子株式会社

Dates

Publication Date

20260508

Application Date

20251105

Priority Date

20241107

Claims (20)

1. 1. A package substrate, comprising: A core having a first surface and a second surface opposite the first surface in a vertical direction, the first and second surfaces being substantially planar, the core comprising glass and a first recess in the first surface; A first bonding layer contacting the first surface of the core and filling the first recess; A through electrode extending from the first surface through the core in the vertical direction, the through electrode being spaced apart from the first recess in a square direction; a first wiring structure on the first bonding layer and contacting the through electrode; a first insulating layer structure on the first bonding layer and at least partially covering the first wiring structure, and A first protective layer which is located on the first insulating layer structure and covers an upper surface of a portion of the first wiring structure.
2. 2. The package substrate of claim 1, wherein a width of the first recess in the horizontal direction is substantially constant in a vertical direction.
3. 3. The package substrate of claim 1, wherein a width of the first recess in the horizontal direction gradually decreases with increasing distance from the first surface of the core in the vertical direction.
4. 4. The package substrate of claim 1, wherein a width of the first recess in the horizontal direction gradually decreases and increases again as a distance from the first surface of the core in the vertical direction increases.
5. 5. The package substrate according to claim 1, wherein a cross section of the first recess in a vertical direction has a stepped shape.
6. 6. The package substrate of claim 1, further comprising a plurality of first recesses spaced apart from each other in the horizontal direction, the first recess being one of the plurality of first recesses.
7. 7. The package substrate of claim 1, wherein the first bonding layer comprises an epoxy and the first insulating layer structure comprises a flavor build film.
8. 8. The package substrate of claim 1, wherein the core further comprises a second recess in a second surface of the core.
9. 9. The package substrate of claim 8, wherein the through electrode extends from the first surface through the core to the second surface in the vertical direction, and Wherein, the packaging substrate further includes: A second bonding layer contacting the second surface of the core and filling the second recess; A second wiring structure on the second bonding layer and contacting the through electrode; a second insulating layer structure on the second bonding layer and at least partially covering the second wiring structure, and And a second protective layer on the second insulating layer structure and covering a lower surface of a portion of the second wiring structure.
10. 10. The package substrate of claim 9, wherein the first recess and the second recess are symmetrically arranged about a line passing through the core in the horizontal direction.
11. 11. A package substrate, comprising: a core comprising glass, the core having a first surface and a second surface opposite the first surface in a vertical direction and a first recess in the first surface; A first bonding layer in the first recess, the first bonding layer including a first organic insulating material; a second bonding layer contacting the first surface of the core and an upper surface of the first bonding layer, the second bonding layer comprising a second organic insulating material different from the first organic insulating material; A through electrode extending from the first surface through the core in the vertical direction, the through electrode being spaced apart from the first recess in a horizontal direction; a first wiring structure on the first bonding layer and contacting the through electrode; a first insulating layer structure on the first bonding layer and at least partially covering the first wiring structure, and A first protective layer which is located on the first insulating layer structure and covers an upper surface of a portion of the first wiring structure.
12. 12. The package substrate of claim 11, wherein a width of the first recess in the horizontal direction gradually decreases with increasing distance from the first surface of the core in the vertical direction.
13. 13. The package substrate of claim 11, wherein the width of the first recess in the horizontal direction gradually decreases and increases again as the distance from the first surface of the core in the vertical direction increases.
14. 14. The package substrate according to claim 11, wherein a cross section of the first recess in the vertical direction has a stepped shape.
15. 15. The package substrate of claim 11, further comprising a plurality of first recesses spaced apart from each other in the horizontal direction, the first recess being one of the plurality of first recesses.
16. 16. The package substrate of claim 11, wherein the through electrode extends from the first surface through the core to the second surface in the vertical direction, Wherein the core further comprises a second recess in the second surface of the core, an Wherein, the packaging substrate further includes: A third bonding layer contacting the second surface of the core and filling the second recess; a second wiring structure on the third bonding layer and contacting the through electrode; a second insulating layer structure on the third bonding layer and at least partially covering the second wiring structure, and And a second protective layer on the second insulating layer structure and covering a lower surface of a portion of the second wiring structure.
17. 17. A semiconductor package, comprising: A package substrate, comprising: A core comprising glass and having a first surface and a second surface opposite the first surface in a vertical direction, the first and second surfaces being substantially planar and the core comprising a first recess in the first surface; A first bonding layer contacting the first surface of the core and filling the first recess; a through electrode extending from the first surface through the core in the vertical direction, the through electrode being spaced apart from the first recess in a horizontal direction; a first wiring structure on the first bonding layer and contacting the through electrode; a first insulating layer structure on the first bonding layer and at least partially covering the first wiring structure, and A first protective layer which is located on the first insulating layer structure and covers an upper surface of the first portion of the first wiring structure; a semiconductor chip on the package substrate, the semiconductor chip including a conductive pad; a first conductive connection in contact with a conductive pad of the semiconductor chip, the conductive connection being electrically connected to a second portion of the first wiring structure, and And a molding member on the package substrate and covering the semiconductor chip and sidewalls of the first conductive connection member.
18. 18. The semiconductor package according to claim 17, wherein the through electrode extends from the first surface through the core to the second surface in the vertical direction, Wherein the core of the package substrate further comprises a second recess in the second surface of the core, Wherein, the packaging substrate further includes: A second bonding layer contacting the second surface of the core and filling the second recess; A second wiring structure on the second bonding layer and contacting the through electrode; a second insulating layer structure on the second bonding layer and at least partially covering the second wiring structure, and A second protective layer on the second insulating layer structure and covering the lower surface of the first portion of the second wiring structure, and Wherein the semiconductor package further includes a second conductive connection in contact with a lower surface of the second portion of the second wiring structure.
19. 19. The semiconductor package according to claim 17, wherein the first recess does not overlap the semiconductor chip in the vertical direction.
20. 20. The semiconductor package of claim 17, further comprising: An interposer between the package substrate and the first conductive connection, the interposer electrically connected to the first wiring structure and the first conductive connection; a heat sink contacting the upper surface of the semiconductor chip, and A heat sink contacting the heat sink.

Description

Package substrate and semiconductor package including the same Cross Reference to Related Applications The present application is based on and claims priority of korean patent application No. 10-2024-0156874 filed on the date of 2024, 11/7 to korean intellectual property office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field Example embodiments relate to a package substrate and a semiconductor package including the same. Background As the area of the package substrate increases, warpage occurs in the package substrate, and a method of increasing the rigidity of the core is required. Disclosure of Invention An aspect is to provide a package substrate having enhanced electrical characteristics. Another aspect is to provide a semiconductor package having enhanced electrical characteristics. According to an aspect of one or more example embodiments, there is provided a package substrate including a core having a first surface and a second surface opposite the first surface in a vertical direction, the first surface and the second surface being substantially planar, the core including glass and a first recess in the first surface, a first bonding layer contacting the first surface of the core and filling the first recess, a through electrode extending from the first surface in the vertical direction through the core, the through electrode being spaced apart from the first recess in a horizontal direction, a first wiring structure on the first bonding layer and contacting the through electrode, a first insulating layer structure on the first bonding layer and at least partially covering the first wiring structure, and a first protective layer on the first insulating layer structure and covering an upper surface of a portion of the first wiring structure. According to another aspect of one or more example embodiments, there is provided a package substrate including a core including glass, the core having a first surface and a second surface opposite the first surface in a vertical direction and a first recess in the first surface, a first bonding layer in the first recess, the first bonding layer including a first organic insulating material, a second bonding layer contacting the first surface of the core and an upper surface of the first bonding layer, the second bonding layer including a second organic insulating material different from the first organic insulating material, a through electrode extending through the core from the first surface in the vertical direction, the through electrode being spaced apart from the first recess in a horizontal direction, a first wiring structure on the first bonding layer and contacting the through electrode, the first insulating layer structure on the first bonding layer and at least partially covering the first wiring structure, and a first protective layer on the first insulating layer structure and covering an upper surface of a portion of the first wiring structure. According to yet another aspect of one or more exemplary embodiments, there is provided a semiconductor package including a package substrate including a core including glass and having a first surface and a second surface vertically opposite the first surface, a first bonding layer contacting the first surface of the core and filling the first recess, a through electrode extending from the first surface in a vertical direction through the core, the through electrode being spaced apart from the first recess in a horizontal direction, a first wiring structure on the first bonding layer and contacting the through electrode, the first insulating layer structure on the first bonding layer and at least partially covering the first wiring structure, and a second surface vertically opposite the first surface, the first surface and the second surface being substantially planar, and the core including a first recess in the first surface, the first bonding layer contacting the first surface of the core and filling the first recess, the through electrode extending from the first surface in a vertical direction through the core, the through electrode being spaced apart from the first recess in a horizontal direction, the first wiring structure on the first bonding layer and contacting the through electrode, the first insulating layer structure on the first wiring structure and at least partially covering the first wiring structure, the first protective layer on the first insulating layer structure and covering an upper surface of a first portion of the first wiring structure, a semiconductor chip on the package substrate including a conductive pad, a first conductive connection chip and a conductive connection chip on the first conductive connection pad and a conductive connection chip and a semiconductor chip. Drawings The above and other aspects will be more apparent upon consideration of the following description taken in conjunction with the accompanying drawings in whic