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CN-122003160-A - Package having an epitaxial layer of an electronic component and a front side connection body with a spacing of less than 50 μm

CN122003160ACN 122003160 ACN122003160 ACN 122003160ACN-122003160-A

Abstract

A package (100) includes a positive side connection body (102) that is at least partially electrically conductive, and an electronic component (104) having an epitaxial layer (118) and assembled with the positive side connection body (102), wherein a distance (d) between the epitaxial layer (118) and the positive side connection body (102) is less than 50 [ mu ] m.

Inventors

  • M. BOHM
  • H-J. Schultzer
  • H. Tois
  • S. ROY
  • M. Grena
  • M. Falkowski
  • S - O Nani Aliyev
  • R. Autremba
  • A. Heinrich
  • E naapet schynige

Assignees

  • 英飞凌科技股份有限公司

Dates

Publication Date
20260508
Application Date
20251103
Priority Date
20241104

Claims (20)

  1. 1. A package (100), comprising: An at least partially electrically conductive front-side connecting body (102), and An electronic component (104) having an epitaxial layer (118) and assembled with the front-side connection body (102); wherein a distance (d) between the epitaxial layer (118) and the front side connection body (102) is less than 50 μm.
  2. 2. The package (100) according to claim 1, wherein a surface of the front side connection body (102) facing the electronic component (104) is curved, in particular curved in a convex manner.
  3. 3. The package (100) according to claim 1 or 2, comprising a conductive connection medium (106) connecting the electronic component (104) with the front side connection body (102), wherein in particular the connection medium (106) is made of a material having a value of at least 60GPa at 20 ℃, more particularly having a young's modulus of at least 100 GPa at 20 ℃.
  4. 4. A package (100) according to any of claims 1 to 3, wherein the front side connection body (102) is a clip (110).
  5. 5. The package (100) of claim 4, wherein a lateral surface of the clip (110) is configured for enhancing stress applied to the electronic component (104).
  6. 6. A package (100) according to any of claims 1 to 3, wherein the front side connection body (102) is a carrier (112), the electronic component (104) being mounted on the carrier (112), for example in a flip-chip configuration on the carrier (112).
  7. 7. The package (100) according to any one of claims 1 to 5, comprising, in addition to the front side connection body (102), a carrier (112), such as a metal layer or a leadframe structure comprising a substrate structure, the electronic component (104) being mounted on the carrier (112).
  8. 8. The package (100) according to claim 6 or 7, wherein a surface of the carrier (112) facing the surface of the electronic component (104) is curved, in particular concavely curved.
  9. 9. The package (100) according to claim 7 or 8, comprising a further electrically conductive connection medium (108) connecting the electronic component (104) with the carrier (112), wherein in particular the further electrically conductive connection medium (108) has a young's modulus value of at least 60GPa at 20 ℃, more particularly at least 100 GPa at 20 ℃.
  10. 10. The package (100) according to any of claims 1 to 3 or 7 to 9, wherein the front side connection body (102) is an interposer, such as a structured interposer, or a substrate (120), such as comprising ceramic, the substrate (120).
  11. 11. The package (100) of any of claims 1 to 10, wherein the electronic component (104) comprises a bulk layer (114) and a metallization layer (116), the epitaxial layer (118) being located between the bulk layer (114) and the metallization layer (116), wherein the epitaxial layer (118) is closer to the frontside connection body (102) than the bulk layer (114).
  12. 12. The package (100) of claim 11, wherein the epitaxial layer (118), the metallization layer (116), the connection medium (106) between the electronic component (104) and the front side connection body (102), and the thickness (d 1, d2, d3, d 4) of the front side connection body (102) have a proportional relationship of 1:at least 2:at least 1:at least 20.
  13. 13. The package (100) of any of claims 1 to 12, comprising at least one of the following features: Wherein the thickness (d 1) of the epitaxial layer (118) is in the range from 5 μm to 70 μm, in particular in the range from 5 μm to 30 μm; Wherein the thickness (d 2) of the metallization layer (116) is in the range from 1 μm to 20 μm, in particular in the range from 2 μm to 10 μm; Wherein the thickness (d 3) of the connection medium (106) is in the range from 0.5 μm to 50 μm, in particular in the range from 1.5 μm to 10 μm, more in particular in the range from 2 μm to 5 μm, and Wherein the thickness (d 4) of the front-side connection body (102) is in the range from 100 μm to 3000 μm.
  14. 14. The package (100) according to any one of claims 1 to 13, wherein the distance (d) between the epitaxial layer (118) and the front-side connection body (102) is less than 20 μιη, in particular less than 10 μιη.
  15. 15. The package (100) of any of claims 1 to 14, wherein the electronic component (104) is at least one of a semiconductor chip, a transistor chip, a power chip, a vertical chip, a silicon carbide chip, a chip with a super junction, a unipolar chip, a bipolar chip, and a chip in a flip chip configuration.
  16. 16. The package (100) of any of claims 3 to 15, comprising at least one of the following features: wherein the connection medium (106) and/or the further connection medium (108) comprises a diffusion bonding material, such as AuSn, niSn, cuSn and/or AgSn; Wherein the connection medium (106) and/or the further connection medium (108) comprises a sintered material, and Wherein the connection medium (106) and/or the further connection medium (108) has a thickness (d 3) of not more than 20 μm, in particular a thickness (d 3) of not more than 10 μm, more in particular a thickness (d 3) of not more than 5 μm.
  17. 17. The package (100) according to any one of claims 1 to 16, wherein the front side connection body (102) and the electronic component (104) are designed such that the stress applied to the electronic component (104) is at least 200 MPa, in particular at least 700 MPa, more in particular at least 1500 MPa.
  18. 18. The package (100) according to any one of claims 1 to 17, wherein the front side connection body (102), the electronic component (104) and an additional carrier (112) are designed for applying stress to the electronic component (104) at two opposite main surfaces of the electronic component (104), a back side of the electronic component (104) being mounted on the additional carrier (112).
  19. 19. A method of manufacturing a package (100), the method comprising: assembling at least partially conductive front-side connection body (102) with an electronic component (104) having an epitaxial layer (118), and -Arranging the front side connection body (102) with respect to the electronic component (104) such that a distance (d) between the epitaxial layer (118) and the front side connection body (102) is less than 50 μm.
  20. 20. The method of claim 19, comprising at least one of the following features: Wherein the method comprises heating the electronic component (104) before and/or during the assembly and allowing the electronic component (104) to cool after the assembly; Wherein the method comprises bending the electronic component (104) through the assembly; wherein the method comprises enhancing the stress permanently applied to the electronic component (104) by the assembly, and Wherein the method comprises adjusting a strain mode of the electronic component (104) to expose different regions of the electronic component (104) to different strain levels, thereby adjusting an on-resistance characteristic of the electronic component (104).

Description

Package having an epitaxial layer of an electronic component and a front side connection body with a spacing of less than 50 μm Technical Field Various embodiments relate generally to packages and methods of manufacturing packages. Background The package may be represented as an electronic component, wherein the electrical connections extend out of the package and may be mounted on an electronic perimeter, such as on a printed circuit board. Packaging costs are an important driving force for industry. Related to this are performance, size and reliability. Different packaging schemes are diverse and must meet the needs of the application. In a packaged transistor electronic component, rdson is a quality parameter that represents "drain-source on-resistance". For example, rdson may indicate the total resistance between the drain and source in a field effect transistor in an "on" state, such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) or a Junction Field Effect Transistor (JFET), i.e., a field effect transistor that may be exclusively voltage controlled and may be used, for example, as an electronically controlled switch or resistor. In particular, rdson may be used as a basis for maximum rated current for electronic components and is also associated with current loss. In short, the lower Rdson, the better. However, rdson of conventional packages may be high. Disclosure of Invention Packages with high electrical performance may be required. In particular, packages with low drain-source on-resistance may be required. According to an exemplary embodiment, a package is provided, the package comprising a front side connection body, the front side connection body being at least partially electrically conductive, and an electronic component having an epitaxial layer and being assembled with the front side connection body, wherein a distance between the epitaxial layer and the front side connection body is less than 50 μm. According to another exemplary embodiment, a method of manufacturing a package is provided, wherein the method comprises assembling together an at least partially conductive front side connection body with an electronic component having an epitaxial layer, and arranging the front side connection body with respect to the electronic component such that a distance between the epitaxial layer and the front side connection body is less than 50 μm. According to an exemplary embodiment, the package (which may be a semiconductor power package) may be provided with a partially or fully conductive front side connection body (such as a clip, a leadframe structure or another more general substrate) that establishes a connection with a front side of the electronic component (where the active area may be formed). The electronic component may comprise an epitaxial layer or an active region facing the front-side connection body. The connection between the front-side connection body and the electronic component may be established, for example, by soldering (holder) or sintering. Advantageously, the distance between the epitaxial layer and the positive side connection body may be less than 50 μm. It has been found that such a small distance between the active region and the connecting body at the front side of the electronic component (e.g. using common interconnect techniques such as soldering, sintering or (more specifically) diffusion soldering) may create a considerable amount of mechanical strain at the front side of the electronic component, which may result in a significant reduction of the drain-source on-resistance. Thus, a package having a low Rdson value and thus having excellent maximum rated current and low current loss can be obtained. Also, in embodiments in which the electronic component does not include a transistor, strain added to the front side of the electronic component may also have a positive effect on the electrical performance of the package. In particular, the semiconductor material may be included in an electronic component having a function of modulating a flow of current. In particular, structures with such semiconductor content may benefit from the proposed strain engineering concepts. Description of further exemplary embodiments Hereinafter, further exemplary embodiments of the package and method will be explained. In the context of the present application, the term "package" may particularly denote an electronic device that may comprise one or more electronic components mounted on a carrier or having another front-side and/or back-side connection body. The component of the package may optionally be at least partially encapsulated by an encapsulant. Further alternatively, one or more electrically conductive interconnect bodies (such as bond wires) may be implemented in the package, for example for electrically coupling the electronic component with the carrier and/or with the leads. In the context of the present application, the term "electronic component" may part