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CN-122003164-A - Memory chip stacking and interconnecting method

CN122003164ACN 122003164 ACN122003164 ACN 122003164ACN-122003164-A

Abstract

The invention belongs to the technical field of chips, and particularly relates to a memory chip stacking and interconnecting method. The method comprises the steps of adjusting the thickness of a wafer and a filling sheet, dividing the wafer and the filling sheet into a single independent storage chip and a single independent filling sheet respectively, attaching the single storage chip to a pretreated glass substrate according to a design, completing the stacking arrangement of multiple chips to form a storage chip stacking body, attaching the single filling sheet to the top of the storage chip stacking body according to the design, leading out a signal pin of each storage chip in the storage chip stacking body through a metal wire, connecting the signal pin to a preset bonding pad of the top filling sheet to obtain a composite structure, molding and packaging the composite structure to form a packaging body, manufacturing a rewiring layer on the surface of the ground packaging body, manufacturing bumps, stripping the pretreated glass substrate, and obtaining the required structure by the residual structure. The invention solves the problems of signal delay, large packaging thickness and RDL alignment deviation by combining the filling sheet bridging structure with the packaging material.

Inventors

  • ZHOU GENGSHEN
  • LIU CHENG
  • CHEN ZHEN
  • WEI XIAOBO
  • WU HENG
  • ZHENG SHUHAO
  • GAO XUAN
  • WU ZHENGDA
  • LI YUAN
  • YU ZHONGXIANG
  • MU JUNHONG
  • LIU CHUNXIAO
  • ZHANG YUE
  • LV DONGBING

Assignees

  • 合肥沛顿存储科技有限公司

Dates

Publication Date
20260508
Application Date
20260409

Claims (10)

  1. 1. A memory chip stacking interconnection method, comprising the steps of: Coating a temporary bonding layer on the surface of the glass substrate to obtain a pretreated glass substrate; the thickness of the wafer and the thickness of the filling sheet are respectively adjusted through a thinning process, and then the wafer and the filling sheet are respectively divided into a single independent storage chip and a single independent filling sheet by adopting a chip cutting process; Mounting a single memory chip on the temporary bonding layer according to the design to complete stacking arrangement of multiple chips to form a memory chip stacking body; attaching a single filler sheet to the top of the stack of memory chips by design; a wire bonding process is adopted, signal pins of each memory chip in the memory chip stacking body are led out through metal wires and are connected to a preset bonding pad of the top filling sheet, and a composite structure is obtained; Molding and packaging the composite structure, and forming a packaging body on the pretreated glass substrate; grinding the packaging body, manufacturing a rewiring layer on the surface of the ground packaging body, and manufacturing salient points on the rewiring layer through a salient point process; The pretreated glass substrate is peeled off, and the rest structure is a structure comprising single or multiple groups of memory chip stacked and interconnected.
  2. 2. The method of claim 1, wherein the temporary bonding layer comprises a release layer and an adhesive layer.
  3. 3. The method of claim 1, wherein the package is polished to remove excess package material on top, wire loops, and portions of the filler pieces.
  4. 4. The method of claim 1, wherein fabricating a redistribution layer on the polished surface of the package body comprises the steps of: and manufacturing a rewiring layer on the surface of the ground packaging body through an RDL process, and redistributing signals on the filling chip bonding pad to preset pin positions.
  5. 5. The method of claim 1, wherein the step of attaching individual memory chips to the temporary bonding layer according to a design to complete the stacked arrangement of the plurality of memory chips to form a memory chip stack comprises the steps of: And mounting the first layer of memory chips on the temporary bonding layer by adopting a step-type offset method, and when the subsequent memory chips are mounted on the lower layer of memory chips, offsetting each layer by a required distance along the long side direction of the lower layer to expose the bonding pads of the lower layer of memory chips, and forming a group of memory chip stacks after the mounting is completed.
  6. 6. The memory chip stack interconnection method of claim 1, wherein the attaching of the single filler sheet to the top of the memory chip stack by design comprises the steps of: a single filler sheet is attached to the top of the two sets of memory chip stacks, each filler sheet connecting the two sets of memory chip stacks.
  7. 7. The method of claim 1, wherein the remaining structures are cut to obtain individual finished chip sets when the remaining structures are interconnected to include multiple groups of memory chip stacks.
  8. 8. The method of claim 1, wherein the step of molding the composite structure to form a package on the pretreated glass substrate comprises the steps of: and (3) carrying out molding treatment on the composite structure with the wire bonding interconnection, completely coating the whole stacking body, the filling sheet and the metal wire by using a packaging material, and forming a packaging body on the pretreated glass substrate.
  9. 9. The method of claim 8, wherein the method of preparing the packaging material comprises the steps of: According to parts by weight, 100 parts of resin, 80-90 parts of curing agent, 3-5 parts of catalyst, 600-800 parts of inorganic filler and 5-6 parts of other auxiliary agents are put into a high-speed mixer, mixed for 5-10 minutes at normal temperature and 500-1000rpm until powder is uniform, mixed powder is obtained, the mixed powder is melted and extruded to obtain a mixed product, and the mixed product is cooled and crushed to obtain the packaging material.
  10. 10. The method of claim 9, wherein the resin comprises biphenyl epoxy resin, the curing agent comprises MHHPA and/or SMA, the catalyst comprises zinc acetylacetonate, the inorganic filler comprises spherical silica powder, the other auxiliary agent comprises at least one of a colorant, a release agent and an accelerator, and the accelerator comprises 2-ethyl-4-methylimidazole.

Description

Memory chip stacking and interconnecting method Technical Field The invention belongs to the technical field of chips, and particularly relates to a memory chip stacking and interconnecting method. Background With the dual increase of bandwidth and volume requirements of mobile terminals and high-performance computing on memory chips, three-dimensional packaging technology is facing a serious technical bottleneck. The prior art mainly has the following two main schemes and defects: 1. conventional Wire Bonding (Wire Bonding) packaging techniques typically employ RDL First or direct Wire Bonding to substrate schemes. The defects are (1) large signal delay, metal wires often need to be connected to the edge of a substrate across a long distance in order to connect the chips stacked in multiple layers, resulting in overlong signal transmission paths, increased parasitic inductance and resistance, and serious influence on high-frequency signal transmission rate and data access efficiency. (2) The thickness of the package is limited, enough wire-arc height must be reserved for preventing the metal wire from being short-circuited, which directly increases the thickness of the package body in the Z-axis direction, and the design requirement of the ultrathin electronic product cannot be met. 2. CHIP FIRST (chip-first mounting) and vertical wire bonding post-grinding technique: In order to solve the thickness problem, the prior art attempts to fix the chip, wire vertically or form the pillar, then grind and expose the metal section after molding, and finally manufacture the re-wiring layer (RDL). The disadvantage is (1) WIRE SWEEP (gold wire offset) causes RDL alignment failure-high viscosity package compound fluids can create large shear forces in the mold cavity during the molding process. The elongated wires are extremely prone to deformation, bending or tilting (i.e., gold wire deflection) under the impact of the compound. (2) Identification is difficult when the RDL lithography process is performed later, the equipment is exposed based on the design coordinates (preset Pad positions). Because the gold wire offset leads to the metal wire top position to take place random offset, the RDL circuit can't connect to the metal wire cross-section accurately, leads to open circuit or contact failure, has greatly reduced the yield. Disclosure of Invention Aiming at the defects of the prior art, the invention provides a memory chip stacking and interconnecting method. A memory chip stacking interconnect method comprising the steps of: Coating a temporary bonding layer on the surface of the glass substrate to obtain a pretreated glass substrate; the thickness of the wafer and the thickness of the filling sheet are respectively adjusted through a thinning process, and then the wafer and the filling sheet are respectively divided into a single independent storage chip and a single independent filling sheet by adopting a chip cutting process; Mounting a single memory chip on the temporary bonding layer according to the design to complete stacking arrangement of multiple chips to form a memory chip stacking body; attaching a single filler sheet to the top of the stack of memory chips by design; a wire bonding process is adopted, signal pins of each memory chip in the memory chip stacking body are led out through metal wires and are connected to a preset bonding pad of the top filling sheet, and a composite structure is obtained; Molding and packaging the composite structure, and forming a packaging body on the pretreated glass substrate; grinding the packaging body, manufacturing a rewiring layer on the surface of the ground packaging body, and manufacturing salient points on the rewiring layer through a salient point process; The pretreated glass substrate is peeled off, and the rest structure is a structure comprising single or multiple groups of memory chip stacked and interconnected. Further, the temporary bonding layer includes a release layer and an adhesive layer. Further, when the package is polished, the excess package material on top, the wire-loop portion of the metal wire, and a portion of the filler piece are removed. Further, a rewiring layer is manufactured on the surface of the ground packaging body, and the method comprises the following steps: and manufacturing a rewiring layer on the surface of the ground packaging body through an RDL process, and redistributing signals on the filling chip bonding pad to preset pin positions. Further, the single memory chip is attached to the temporary bonding layer according to the design, the stacking arrangement of the multiple chips is completed, and a memory chip stacking body is formed, and the method comprises the following steps: And mounting the first layer of memory chips on the temporary bonding layer by adopting a step-type offset method, and when the subsequent memory chips are mounted on the lower layer of memory chips, offsetting each layer by a required dista