CN-122003166-A - Packaging structure and packaging method

Abstract

In the packaging structure, the first surface and the second surface of the chip structure are electrically connected, the conducting structure is electrically connected with the first connecting end at the other side of the bonding area through the first substrate, the chip structure, the conducting structure and the second substrate, the electric connection between the first connecting ends at the two sides of the bonding area and between the first connecting ends and the chip structure is realized, the electric connection in the vertical direction is realized between the first surface and the second surface of the chip structure and between the conducting structure, so that stray inductance is reduced, and in addition, the area occupied by the electric connection path in the first substrate can be reduced through the electric connection path of the chip structure, the second substrate and the conducting structure, the area of the first substrate for radiating is increased, the area of the first substrate for bonding the chip structure is also increased, the bonding quantity of the chip structure is correspondingly improved, the outflow capacity of the packaging structure is improved, and the performance of the packaging structure is optimized.

Inventors

• Jin Shuiying

Assignees

• 长电科技管理有限公司

Dates

Publication Date

20260508

Application Date

20260211

Claims (20)

1. 1. A package structure, comprising: The first substrate comprises a bonding area and connecting areas positioned at two sides of the bonding area; The first connecting end is bonded on the connecting area and is electrically connected with the first substrate; The chip structure comprises a first surface and a second surface which are opposite to each other, wherein the first surface is bonded with the first substrate, and the first surface is electrically connected with the first connecting end positioned at one side of the bonding area through the first substrate; The conductive structure is bonded on the bonding area exposed by the chip structure and is electrically connected with the first substrate, and the conductive structure is electrically connected with a first connecting end positioned at the other side of the bonding area through the first substrate; and the second substrate is bonded on the second surface of the chip structure and the top of the conductive structure and is electrically connected with the second surface of the chip structure and the conductive structure.
2. 2. The package structure of claim 1, wherein a projection of the second substrate onto the first substrate exposes the connection region.
3. 3. The package structure of claim 1 or 2, wherein the first connection terminal comprises a power terminal.
4. 4. The package structure of claim 3, wherein the first connection terminal is a block-shaped structure.
5. 5. The package of claim 3 wherein said power terminal on one side of said bond pad is configured to be an ac power terminal and said power terminal on the other side of said bond pad is configured to be a dc power terminal.
6. 6. The package structure of claim 5, wherein the dc power terminals comprise a positive dc power terminal and a negative dc power terminal.
7. 7. The package structure of claim 2, further comprising a package layer overlying the first substrate and filling a space between the first substrate and the second substrate, the package layer exposing the first connection terminal and a top of the second substrate.
8. 8. The package structure of claim 7, wherein a gap is provided between a side of the first connection end and the encapsulation layer.
9. 9. The package structure of claim 1, wherein the chip structure includes a chip and an electrical connection layer on the chip, the electrical connection layer being electrically connected to the chip.
10. 10. The package structure of claim 9, wherein a side of the chip opposite the electrical connection layer is the first side and a side of the electrical connection layer opposite the chip is the second side.
11. 11. The package structure of claim 1, wherein the conductive structure comprises a columnar structure.
12. 12. The package structure of claim 1, wherein the material of the conductive structure comprises copper.
13. 13. The package structure of claim 1, wherein the first substrate comprises a first interconnect layer; the first connecting end, the chip structure and the conductive structure are bonded on the first interconnection layer; the first interconnection layer is electrically connected with the first surface and a first connecting end positioned at one side of the bonding area; The first interconnection layer is electrically connected with the conductive structure and a first connection end positioned on the other side of the bonding area.
14. 14. The package structure of claim 1, wherein the second substrate comprises a second interconnect layer bonded to the second side of the chip structure and on top of the conductive structure, the second interconnect layer electrically connecting the second side of the chip structure and the conductive structure.
15. 15. The package structure of claim 1, further comprising a second connection terminal bonded to the connection region exposed by the first connection terminal, the second connection terminal comprising a signal terminal.
16. 16. The package structure of claim 15, wherein the second connection end comprises a pin structure.
17. 17. A method of packaging, comprising: providing a first substrate, wherein the first substrate comprises a bonding area and connecting areas positioned at two sides of the bonding area; Providing one or more chip structures, the chip structures including first and second opposed faces; Bonding one or more chip structures, conductive structures and first connection terminals on the first substrate; the first surface of the chip structure is bonded on the bonding area of the first substrate and is electrically connected with the first substrate, the conductive structure is bonded on the bonding area exposed by the chip structure and is electrically connected with the first substrate, and the first connecting end is bonded on the connecting area and is electrically connected with the first substrate, wherein the first connecting end positioned on one side of the bonding area is electrically connected with the first surface through the first substrate, and the first connecting end positioned on the other side of the bonding area is electrically connected with the conductive structure through the first substrate; And bonding a second substrate on the second surface of the chip structure and the top of the conductive structure, wherein the second substrate is electrically connected with the second surface of the chip structure and the conductive structure.
18. 18. The packaging method of claim 17, wherein in the step of bonding a second substrate on the second side of the chip structure and on top of the conductive structure, a projection of the second substrate onto the first substrate exposes the connection region.
19. 19. The packaging method of claim 17 or 18, wherein the first connection terminal comprises a power terminal.
20. 20. The packaging method of claim 17, further comprising bonding one or more of a chip structure, a conductive structure, and a first connection terminal on the first substrate, and after bonding a second substrate on a second side of the chip structure and on top of the conductive structure, covering a packaging layer on the first substrate, the packaging layer filling a space between the first substrate and the second substrate and exposing the first connection terminal and the top of the second substrate.

Description

Packaging structure and packaging method Technical Field The present disclosure relates to semiconductor devices, and particularly to a packaging structure and a packaging method. Background With the rapid development of electronic technology, power electronics plays an increasingly important role in various application fields. In order to meet the requirements of high power density and high reliability, the packaging technology of the power module becomes one of the key technologies. Wherein, the heat dissipation capacity of the power module can influence the working performance and the service life thereof. To improve the heat dissipation effect, a double-sided heat dissipation package structure has been developed. Compared with a single-sided heat dissipation packaging structure, the double-sided heat dissipation packaging structure is provided with the heat conduction substrates on two sides of the chip, and accordingly heat can be dissipated from the two sides of the chip, so that the heat dissipation efficiency of the packaging structure is improved. However, the performance and heat dissipation efficiency of the current package structure still need to be improved. Disclosure of Invention The invention provides a packaging structure and a packaging method, which are used for improving the performance of the packaging structure. In order to solve the problems, the invention provides a packaging structure which comprises a first substrate, one or more chip structures, a second substrate and a conductive structure, wherein the first substrate comprises a bonding area and connecting areas positioned on two sides of the bonding area, the first connecting ends are bonded on the connecting areas and are electrically connected with the first substrate, the one or more chip structures are bonded on the bonding area of the first substrate, the chip structures comprise a first surface and a second surface which are opposite, the first surface is bonded with the first substrate, the first surface is electrically connected with the first connecting ends positioned on one side of the bonding area through the first substrate, the conductive structure is bonded on the bonding area exposed by the chip structures and is electrically connected with the first substrate, the conductive structure is electrically connected with the first connecting ends positioned on the other side of the bonding area through the first substrate, the second substrate is bonded on the second surface of the chip structures and the top of the conductive structure, and the second substrate is electrically connected with the second surface of the chip structures. The invention provides a packaging method, which comprises the steps of providing a first substrate, comprising a bonding area and connecting areas positioned on two sides of the bonding area, providing one or more chip structures, wherein the chip structures comprise a first surface and a second surface which are opposite to each other, bonding one or more chip structures, a conductive structure and a first connecting end on the first substrate, wherein the first surface of the chip structure is bonded on the bonding area of the first substrate and is electrically connected with the first substrate, the conductive structure is bonded on the bonding area exposed by the chip structure and is electrically connected with the first substrate, the first connecting end is bonded on the connecting area and is electrically connected with the first substrate, the first connecting end positioned on one side of the bonding area is electrically connected with the first surface through the first substrate, the first connecting end positioned on the other side of the bonding area is electrically connected with the conductive structure through the first substrate, and the conductive structure is electrically connected with the second substrate on the top of the second surface of the chip structure and the second substrate. Compared with the prior art, the technical scheme of the invention has the following advantages: According to the packaging structure provided by the embodiment of the invention, the first surface and the second surface of the chip structure are electrically connected, and the first surface is electrically connected with the first connecting end positioned at one side of the bonding area through the first substrate; the packaging structure further comprises a conductive structure, the conductive structure is electrically connected with the first connecting end at the other side of the bonding area through the first substrate, the second substrate is electrically connected with the conductive structure and the chip, so that the conductive structure is electrically connected between the first connecting ends at the two sides of the bonding area and between the conductive structure and the chip structure through the first substrate, the chip structure, the conductive structure and the