CN-122003167-A - Multi-chip in-situ stacking structure, stacking method and system thereof, and chips

CN122003167ACN 122003167 ACN122003167 ACN 122003167ACN-122003167-A

Abstract

The invention relates to the technical field of chip stacking, and provides a multi-chip in-situ stacking structure, a stacking method, a system and chips thereof, which comprise using a FOW film as a single connecting bonding medium to replace the traditional DAF bottom chip film, the structure of the structure comprises a substrate and a plurality of layers of chips which are stacked in sequence, wherein each layer of chips are electrically interconnected with the substrate through leads and are connected with the substrate or other chips through FOW films, the leads can pass through the FOW films through heating, and stable adhesion is realized after solidification. In the process, FOW films are pre-attached to the back of the chip, the chips are sequentially stacked after dicing, and each layer of stacked chips is heated and cured and then wire bonding is performed. By adopting a single FOW film, the process control elements are reduced, the production flow is simplified, the production efficiency of products is effectively improved, and meanwhile, the stacking stability and the electrical connection reliability of chips are ensured.

Inventors

SONG YIXIONG
YANG ZHUORAN
LUO JIRUI

Assignees

成都天奥电子股份有限公司

Dates

Publication Date: 20260508
Application Date: 20260205

Claims (9)

1. A multi-chip in-situ stacking structure, comprising: a substrate; At least two layers of chips, wherein a plurality of layers of chips are sequentially stacked on the substrate, and each layer of chips is electrically interconnected with the substrate through leads; any chip is connected with other chips or the substrate through the FOW film, the FOW film allows leads to pass through after heating and realizes bonding and fixing between the chip and the chip or between the chip and the substrate after solidification.
2. The multi-chip in-situ stacking structure of claim 1, wherein projections of the chips of each layer onto the substrate are completely overlapped to realize the same-size stacking.
3. The multi-chip in-situ stacked structure of claim 1, wherein the FOW film has a heating temperature of 115-125 ℃.
4. A multi-chip in-situ stacking method for fabricating a multi-chip in-situ stacking structure as claimed in any one of claims 1 to 3, said method comprising: S101, obtaining a first wafer, thinning the first wafer until the height meeting stacking requirements is achieved, and attaching a FOW film on the back surface of the first wafer; S102, dicing the first wafer attached with the FOW film to obtain a plurality of independent first chips with the FOW film attached to the back surface; s103, placing the FOW film attached to the back surface of the first chip at a specified position of the substrate in the direction of the substrate; S104, heating and curing the first chip placed on the substrate to fix the first chip with the substrate through the FOW film; S105, conducting wire bonding on the first chip after curing to form electrical connection with the substrate; S106, acquiring a second chip, attaching a FOW film on the back surface of the second chip, preheating the second chip to 115-125 ℃ with the FOW film attached on the back surface of the second chip facing the direction of the first chip, enabling the FOW film to penetrate through a first chip lead wire, and stacking the FOW film on the first chip; S107, heating and curing the second chips stacked, so that the second chips are fixed on the first chips through the FOW film; S108, conducting wire bonding on the second chip after curing to form electrical connection with the substrate; And S109, repeating the steps S106 to S108, and continuously stacking the subsequent chips with the FOW films attached on the back surfaces on the second chips in the same manner until the preset stacking layer number is reached.
5. The method of claim 4, wherein the step of placing the first chip at a specified position on the substrate with the FOW film attached to the back surface thereof facing the substrate, comprises: calibrating bonding pressure, vertical direction and down-pressure height of a bonding head of the die bonding equipment and the substrate; controlling the bonding head to pick up the first chip and lifting the first chip to a safe height; Controlling the bonding head to carry the first chip to descend from the safe height to the slow release height at a first speed; controlling the bonding head to descend from the slow release height to the patch height at a second speed, so that the FOW film on the back of the first chip is contacted with the substrate; applying preset bonding pressure to the first chip at the patch height, keeping preset contact time, and simultaneously destroying vacuum adsorption of the bonding head to the first chip through weak blowing so as to release the first chip to the substrate; controlling the bonding head to rise from the patch height to the slow release height at a second speed; and controlling the bonding head to be lifted from the slow release height to the safety height at a first speed.
6. A multi-chip in situ stacking method as described in any of claims 4 or 5, wherein, the step of heating and curing the first chip placed on the substrate specifically includes: Controlling a heating device to heat the FOW film on the back of the first chip according to a preset curing temperature curve; The preset solidification temperature curve comprises a first heating stage, a first heat preservation stage, a second heating stage, a second heat preservation stage and a cooling stage which are sequentially carried out, wherein the first heating stage is used for increasing the temperature from an initial temperature to a first temperature at a first preset speed in a first preset time, the first heat preservation stage is used for keeping the first temperature for a second preset time so as to release bubbles, the second heating stage is used for increasing the temperature to a second temperature at a second preset speed in a third preset time, the second heat preservation stage is used for keeping the second temperature for a fourth preset time, and the cooling stage is used for reducing the temperature to the initial temperature at a third preset speed in a fifth preset time.
7. The multi-chip in-situ stacking method of claim 6, wherein said second predetermined time is determined by the time taken for the bubbles to be completely discharged.
8. A multi-chip in-situ stacking system, the system comprising: The first wafer mounting module is used for obtaining a first wafer, thinning the first wafer until the height meeting the stacking requirement is reached, and mounting a FOW film on the back surface of the first wafer; the scribing module is used for scribing the first wafer attached with the FOW film to obtain a plurality of independent first chips with the FOW film attached to the back surface; A placement module, configured to place the first chip at a specified position of the substrate in a direction in which the FOW film attached to the back surface of the first chip faces the substrate; the first heating and curing module is used for heating and curing the first chip arranged on the substrate, so that the first chip is fixed with the substrate through the FOW film; The first bonding module is used for conducting wire bonding on the solidified first chip to form electrical connection with the substrate; the stacking module is used for obtaining a second chip, and the back surface of the second chip is attached with the FOW film; stacking the second chip on the first chip in a direction that the FOW film attached to the back surface of the second chip faces the first chip; a second heat curing module for heat curing the stacked second chips to fix the second chips to the first chips through the FOW film; the second bonding module is used for conducting wire bonding on the cured second chip to form electrical connection with the substrate; And the circulation module is used for repeating the stacking module, the second heating and curing module and the second bonding module, and continuously stacking the subsequent chips with the FOW films attached to the back surfaces on the second chips in the same mode until the number of the preset stacking layers is reached.
9. A memory chip, wherein a dual-layer or multi-layer stack is realized by using the multi-chip in-situ stack structure as claimed in any one of claims 1 or 2, wherein all chips are of the same type, and a FOW film is used between adjacent chips and between the chips and a substrate during the stack.

Description

Multi-chip in-situ stacking structure, stacking method and system thereof, and chips Technical Field The invention relates to the technical field of chip stacking, in particular to a multi-chip in-situ stacking structure, a stacking method, a system and chips thereof. Background The statements in this section merely provide background information related to the present disclosure and may not constitute prior art. Currently, memory chips are rapidly developing toward high capacity, high speed, high frequency, low power consumption and miniaturization, and for packaging more chips in smaller volumes, the three-dimensional stacked packaging mode is increasingly used in the packaging structure of memory chips. Compared with the traditional two-dimensional package, the three-dimensional stacked package not only can effectively reduce the package volume and improve the service efficiency and storage density of the substrate, but also can shorten the wiring length and the signal transmission path, reduce the time delay of the system and the power consumption of the chip, and has more excellent technical characteristics and economy. However, three-dimensional stacking techniques currently employing wire interconnection processes have mainly five typical structures, and all have significant drawbacks. The pyramid stacking structure (shown in figure 8) is affected by area decreasing effect, the total stacking layer number is limited and is usually not more than 5 layers, meanwhile, the leads of the upper chip and the lower chip are different in length, the conditions of inconsistent time sequence and unstable delay are easy to occur, the length equalization is required to be carried out on the design level of the substrate, the design difficulty is high, the product performance is limited by the longest lead, and the optimal performance of the core particle is difficult to fully play; the occupation area of the staggered stacking structure (shown in fig. 9) is usually 125% of the area of the bottom chip, the staggered area is further enlarged along with the increase of the stacking layer number, the miniaturization development of products is not facilitated, in addition, the occupation area of the staggered stacking structure (shown in fig. 10) is larger than the staggered stacking area due to the fact that the occupation area of the staggered stacking structure (shown in fig. 10) is equal to the area of the chips, the occupation area of the staggered stacking structure (shown in fig. 10) is up to 150% of the area of the bottom chip, the occupation area of the staggered stacking structure is larger than the staggered stacking structure due to the fact that the length and width of the upper chip and the lower chip are staggered, the substrate bonding pads are generally required to be arranged around, the extremely high requirement is provided for substrate wiring, and the problem that the bonding pads are suspended is also caused, the occupation area of the overhead stacking structure (shown in fig. 11) is equal to the area of the chips, but an intermediate overhead layer (Spacer) is required to be added between each layer of chips in the vertical direction, the Spacer patch procedure is additionally added in the process flow, the total thickness of the products is higher than that the other types, the space utilization in the vertical direction is lower, the DAF+FOW film type same-size stacking structure (shown in figure 12) has the same occupied area as a single chip, wherein a bottom chip adopts a chip bonding film (DIE ATTACH FILM, DAF) as a bottom layer fixing adhesive, and a lead penetrating back Film (FOW) is adopted for stacking from a second chip. Therefore, there is a need for a multi-chip in-situ stacking structure, a stacking method, a system and a chip thereof, which simplify the production process of multi-chip in-situ stacking and improve the production efficiency of the product. Disclosure of Invention The present invention is directed to a multi-chip in-situ stacking structure, a stacking method, a system and a chip thereof, so as to improve the above-mentioned problems. In order to achieve the above purpose, the technical scheme adopted by the invention is as follows: in a first aspect, the present application provides a multi-chip in-situ stacked structure comprising: a substrate; At least two layers of chips, wherein the layers of chips are sequentially stacked on the substrate, and each layer of chips is electrically interconnected with the substrate through leads; the FOW film allows the lead wire to pass through after heating, and realizes bonding and fixing between chips or between chips and substrates after solidification. Further, projections of the chips of each layer on the substrate are completely overlapped, so that the same-size stacking is realized. Further, the heating temperature of the FOW film is 115-125 ℃. In a second aspect, the present application also provides a multi-chip in-si