CN-122003637-A - Array substrate, display panel, display device and driving method

CN122003637ACN 122003637 ACN122003637 ACN 122003637ACN-122003637-A

Abstract

An array substrate, a display panel, a display device and a driving method. The array substrate comprises a substrate (1), a plurality of grid lines (2), a plurality of data lines (3), at least one data line (3) of the data lines (3) comprises first data portions (31) and second data portions (32) which are alternately distributed along a second direction, extension lines of the two first data portions (31) on two sides of the second data portions (32) are not overlapped in the second direction, the maximum length of the pixel electrodes (4) in the first direction is larger than the maximum length of the pixel electrodes (4) in the second direction, and the orthographic projection of the pixel electrodes (4) in the substrate (1) is overlapped with at least part of the orthographic projection of the grid lines (2) in the substrate (1), a plurality of first common electrodes (65) extend along the second direction and are disconnected at the position crossing the grid lines (2), and the orthographic projection of the first common electrodes (65) in the substrate (1) at least partially covers a gap between the data lines (3) and the pixel electrodes (4).

Inventors

YANG GUIDONG
XIAO FENG
ZHU WEI
DENG YU
SHI XINPING
QI XIAOJING

Assignees

京东方科技集团股份有限公司
成都京东方显示科技有限公司

Dates

Publication Date: 20260508
Application Date: 20250115
Priority Date: 20240227

Claims (20)

An array substrate, comprising: A substrate; A plurality of gate lines located at one side of the substrate, the plurality of gate lines extending in a first direction; A plurality of data lines which are positioned on the same side of the substrate as the plurality of gate lines, wherein the plurality of data lines extend along a second direction, and at least one data line in the plurality of data lines comprises first data parts and second data parts which are alternately distributed along the second direction; A plurality of pixel electrodes, the maximum length of the pixel electrodes in the first direction being greater than the maximum length in the second direction, and the orthographic projection of the plurality of pixel electrodes on the substrate overlapping at least part of the orthographic projection of the grid line on the substrate; And a plurality of first common electrodes extending in the second direction and disconnected at positions crossing the gate lines, the first common electrodes being projected on the substrate at least partially covering gaps between the data lines and the pixel electrodes.
The array substrate of claim 1, wherein the array substrate further comprises a first common trace extending along the first direction, wherein the first common trace is orthographic projected on the substrate through the pixel electrode in a center region of the orthographic projection of the substrate; The first common electrode is connected to the first common wiring.
The array substrate of claim 1 or 2, wherein the array substrate comprises a second common wire group extending along the second direction, wherein the second common wire group is disconnected at a position crossing the grid wires, and comprises a first sub-common wire and a second sub-common wire which are arranged along the first direction, wherein the length of the first sub-common wire in the second direction is smaller than the length of the second sub-common wire in the second direction, and the first sub-common wire and the second sub-common wire are alternately arranged in the second direction; The array substrate further comprises a common compensation part connected to one side, far away from the second sub-common wiring, of the first sub-common wiring, and the first common electrode comprises the first sub-common wiring and the common compensation part.
The array substrate of claim 3, wherein a side of the first common electrode facing the second sub-common wiring has a fifth outer edge extending in the second direction, and extension lines of the fifth outer edges of two adjacent first common electrodes in the second direction do not coincide.
The array substrate of any one of claims 1 to 4, wherein the first common electrode comprises a trace body, and a trace protrusion extending from at least one side of the trace body along the second direction; and the orthographic projection of the wiring convex part on the substrate and the orthographic projection of the data line on the substrate are not overlapped.
The array substrate of any one of claims 1 to 5, wherein the front projection of the first common electrode on the substrate does not overlap with the front projection of the data line on the substrate, and has an overlapping region with the portion of the pixel electrode on the front projection of the substrate.
The array substrate of any one of claims 1 to 5, wherein a maximum length of the first common electrode in the second direction is smaller than a minimum distance between two adjacent gate lines in the second direction; the width of the first common electrode in the first direction is larger than the width of the second sub-common wiring in the first direction.
The array substrate of any one of claims 1 to 7, wherein at least one gate line of the plurality of gate lines comprises a plurality of gate line groups sequentially distributed along a first direction, wherein the gate line groups comprise first gate line parts, second gate line parts and third gate line parts, wherein the first gate line parts and the second gate line parts are positioned between and connected, and extension lines of the first gate line parts and the second gate line parts do not coincide, and extension lines of the third gate line parts intersect with the first direction; And the orthographic projection of the plurality of pixel electrodes on the substrate is overlapped with the orthographic projection of the first grid line part and the second grid line part on the substrate at least partially.
The array substrate of claim 8, wherein the third gate line portion extends along the third direction, the third direction intersecting the first direction and the second direction.
The array substrate of claim 8 or 9, wherein a length of the gate line group in the first direction is substantially equal to a length of the pixel electrode in the first direction.
The array substrate of claim 10, wherein a length of the first gate line portion in the first direction is less than or equal to a maximum length of the second gate line portion in the first direction.
The array substrate of any one of claims 1 to 11, wherein the gate lines further comprise gate line connection parts between and connecting the adjacent gate line groups, the gate line connection parts extending in the first direction, and extension lines between the first and second gate line parts.
The array substrate of any one of claims 1 to 12, wherein, in the same gate line group, an orthographic projection of the first gate line portion on the substrate is covered by an orthographic projection of one of the pixel electrodes on the substrate, and an orthographic projection of the second gate line portion on the substrate is covered by an orthographic projection of another adjacent one of the pixel electrodes on the substrate in the second direction.
The array substrate of any one of claims 1 to 7, wherein the orthographic projection of the gate line on the substrate is linear.
The array substrate of any one of claims 1 to 14, wherein the second data part comprises a first sub data part, a second sub data part, and a third sub data part, wherein the first sub data part extends along the first direction; One end of the first sub data part is connected with one end of the second sub data part, the other end of the first sub data part is connected with one end of the third sub data part and one first data part, and the other end of the second sub data part is connected with the other first data part.
The array substrate of claim 15, wherein the first sub data portions of two adjacent second data portions and the first data portion between two adjacent second data portions form a groove; The first common electrode is positioned in the orthographic projection of the substrate at least partially and the groove is positioned in the orthographic projection of the substrate.
The array substrate of claim 15 or 16, wherein the orthographic projection of the first data portion on the substrate is located at a region between orthographic projections of two adjacent pixel electrodes on the substrate in the first direction; And the orthographic projection of the second data part on the substrate and the orthographic projection of the grid line on the substrate have an overlapping area.
The array substrate of any one of claims 15-17, wherein the array substrate further comprises a plurality of transistors, wherein at least one transistor of the plurality of transistors comprises a control electrode, an active pattern, and first, second and third electrodes sequentially distributed along the first direction, wherein the front projections of the first, second and third electrodes on the substrate all have an overlapping area with the front projection of the control electrode on the substrate, and wherein the front projections of the first, second and third electrodes on the substrate all have an overlapping area with the front projection of the active pattern on the substrate; the first pole multiplexes the second sub data section; the third pole multiplexes the third sub data section; The second pole comprises a second pole first part extending along the second direction and a second pole lap joint part connected with one end of the second pole first part, wherein the second pole first part is positioned between the orthographic projection of the second sub-data part and the orthographic projection of the third sub-data part on the substrate.
The array substrate of claim 18, wherein a length of the second electrode overlap portion in the second direction is substantially equal to a length of the first data portion in the second direction.
The array substrate of claim 18 or 19, wherein a width of the second pole landing part in the first direction is greater than a width of the second pole first part in the first direction.

Description

Array substrate, display panel, display device and driving method Cross Reference to Related Applications The present application claims priority from international application filed on day 27 of 2024, 02, under application number PCT/CN2024/078797, entitled "array substrate, display panel, display device and driving method", the entire or part of which is incorporated herein by reference. Technical Field The disclosure relates to the field of semiconductor technology, and in particular, to an array substrate, a display panel, a display device and a driving method. Background Compared with the conventional pixel driving structure with one Gate line and one data line (1G 1D), a special pixel driving structure is sometimes adopted to reduce data lines and increase scanning lines, and the special pixel driving structure is a double Gate pixel driving structure (Dual Gate) and a triple Gate pixel driving structure (TRIPLE GATE). In the display panel with the same size, compared with the 1G1D pixel driving structure, the three-Gate pixel driving structure has two times of row scanning lines, and the data lines become one third of the original data lines, if the Gate driving circuit is integrated in the driving structure of the display panel (GOA), the cost of the driving circuit is not required to be increased additionally when the number of the scanning lines is increased, and the number of the data lines is reduced to reduce the number of the driving ICs, so that the cost advantage is achieved. Disclosure of Invention The embodiment of the disclosure provides an array substrate, a display panel, a display device and a driving method. The array substrate includes: A substrate; A plurality of gate lines located at one side of the substrate, the plurality of gate lines extending in a first direction; A plurality of data lines which are positioned on the same side of the substrate as the plurality of gate lines, wherein the plurality of data lines extend along a second direction, and at least one data line in the plurality of data lines comprises first data parts and second data parts which are alternately distributed along the second direction; A plurality of pixel electrodes, the maximum length of the pixel electrodes in the first direction being greater than the maximum length in the second direction, and the orthographic projection of the plurality of pixel electrodes on the substrate overlapping at least part of the orthographic projection of the grid line on the substrate; And a plurality of first common electrodes extending in the second direction and disconnected at positions crossing the gate lines, the first common electrodes being projected on the substrate at least partially covering gaps between the data lines and the pixel electrodes. In one possible implementation, the array substrate further comprises a first common wiring extending along the first direction, wherein the first common wiring is orthographic projected on the substrate and passes through the pixel electrode to be orthographic projected on a central area of the substrate; The first common electrode is connected to the first common wiring. In one possible implementation, the array substrate comprises a second public wire group extending along the second direction, wherein the second public wire group is disconnected at a position crossing the grid wire, and comprises a first sub public wire and a second sub public wire which are arranged along the first direction, wherein the length of the first sub public wire in the second direction is smaller than that of the second sub public wire, and the first sub public wire and the second sub public wire are alternately arranged in the second direction; The array substrate further comprises a common compensation part connected to one side, far away from the second sub-common wiring, of the first sub-common wiring, and the first common electrode comprises the first sub-common wiring and the common compensation part. In a possible implementation manner, a side of the first common electrode facing the second sub-common wiring is provided with a fifth outer edge extending along the second direction, and extension lines of the fifth outer edges of two adjacent first common electrodes in the second direction are not overlapped. In one possible embodiment, the first common electrode includes a trace body, and a trace protrusion extending from at least one side of the trace body along the second direction; and the orthographic projection of the wiring convex part on the substrate and the orthographic projection of the data line on the substrate are not overlapped. In one possible embodiment, the front projection of the first common electrode on the substrate does not overlap with the front projection of the data line on the substrate, and has an overlapping region with the portion of the pixel electrode on the front projection of the substrate. In a possible embodiment, a maximum length of the first com