CN-122003657-A - Adaptive memory frequency control and method for computing devices

Abstract

Aspects of the present disclosure relate to techniques and apparatus for implementing adaptive frequency control of memory banks in computing devices. The frequency of the memory banks may be independently controlled based on the data access patterns of the memory banks to optimize performance and power consumption of the memory banks. In some aspects, a computing device may save energy by reducing the frequency of one or more memory banks storing infrequently accessed data while maintaining high performance of one or more memory banks for frequently accessed data.

Inventors

• ZHANG YANSONG
• WANG ZIXIANG
• LUO WEIZHANG
• ZHANG HAIHE
• FANG WUMEI
• WANG XIANCHAO

Assignees

• 高通股份有限公司

Dates

Publication Date

20260508

Application Date

20231012

Claims (20)

1. 1. A computing device, the computing device comprising: a plurality of memory banks, and One or more processors coupled to the plurality of memory banks, The one or more processors are configured to: Storing data in a plurality of memory banks; identifying a data access pattern of the data stored in the plurality of memory banks, and The throughput of one or more of the plurality of memory banks is adjusted based on the data access pattern of the data such that two or more of the plurality of memory banks have different throughputs.
2. 2. The computing device of claim 1, wherein the one or more processors are further configured to: setting a first memory bank of the plurality of memory banks to a first clock frequency corresponding to a first throughput, and A second memory bank of the plurality of memory banks is set to a second clock frequency corresponding to a second throughput different from the first throughput.
3. 3. The computing device of claim 2, wherein the data access pattern comprises: A first data access rate of the first memory bank corresponding to a first application, and A second data access rate of the second memory bank corresponding to a second application, the first data access rate being different from the second data access rate.
4. 4. The computing device of claim 2, wherein the data access pattern comprises: a first data access rate of the first memory bank corresponding to a first portion of the application, and A second data access rate of the second memory bank corresponding to a second portion of the application, the first data access rate being different from the second data access rate.
5. 5. The computing device of claim 1, wherein the one or more processors are further configured to: increasing a clock frequency of a first memory bank of the plurality of memory banks, the first memory bank including first data, and The method includes reducing a clock frequency of a second memory bank of the plurality of memory banks, the second memory bank including second data, wherein a data access rate of the first data is greater than a data access rate of the second data.
6. 6. The computing device of claim 1, wherein the one or more processors are further configured to: Monitoring a data access rate of a portion of the data stored in a first memory bank of the plurality of memory banks, and The portion of the data is moved between the first and second ones of the plurality of memory banks based on the data access rate of the portion of the data.
7. 7. The computing device of claim 6, wherein the one or more processors are further configured to: The portion of the data is moved from the first memory bank to the second memory bank in response to the data access rate of the portion of the data being greater than a predetermined threshold, the second memory bank having a throughput greater than the first memory bank.
8. 8. The computing device of claim 6, wherein the one or more processors are further configured to: in response to the data access rate of the portion of the data being less than a predetermined threshold, the portion of the data is moved from the first memory bank to the second memory bank, the second memory bank having a throughput less than the first memory bank.
9. 9. The computing device of claim 6, wherein the one or more processors are further configured to: determining a number of times a flag of the first memory bank is set within a predetermined period of time, the flag indicating an access status of the first memory bank, and The data access rate of the data stored in the first memory bank is determined based on the number of times the flag is set.
10. 10. A method of operating a computing device, the method comprising: Storing data in a plurality of memory banks; identifying a data access pattern of the data stored in the plurality of memory banks, and The throughput of one or more of the plurality of memory banks is adjusted based on the data access pattern of the data such that two or more of the plurality of memory banks have different throughputs.
11. 11. The method of claim 10, the method further comprising: setting a first memory bank of the plurality of memory banks to a first clock frequency corresponding to a first throughput, and A second memory bank of the plurality of memory banks is set to a second clock frequency corresponding to a second throughput different from the first throughput.
12. 12. The method of claim 11, wherein the data access pattern comprises: A first data access rate of the first memory bank corresponding to a first application, and A second data access rate of the second memory bank corresponding to a second application, the first data access rate being different from the second data access rate.
13. 13. The method of claim 11, wherein the data access pattern comprises: a first data access rate of the first memory bank corresponding to a first portion of the application, and A second data access rate of the second memory bank corresponding to a second portion of the application, the first data access rate being different from the second data access rate.
14. 14. The method of claim 10, the method further comprising: increasing a clock frequency of a first memory bank of the plurality of memory banks, the first memory bank including first data, and The method includes reducing a clock frequency of a second memory bank of the plurality of memory banks, the second memory bank including second data, wherein a data access rate of the first data is greater than a data access rate of the second data.
15. 15. The method of claim 10, the method further comprising: Monitoring a data access rate of a portion of the data stored in a first memory bank of the plurality of memory banks, and The portion of the data is moved between the first and second ones of the plurality of memory banks based on the data access rate of the portion of the data.
16. 16. The method of claim 15, the method further comprising: The portion of the data is moved from the first memory bank to the second memory bank in response to the data access rate of the portion of the data being greater than a predetermined threshold, the second memory bank having a throughput greater than the first memory bank.
17. 17. The method of claim 15, the method further comprising: in response to the data access rate of the portion of the data being less than a predetermined threshold, the portion of the data is moved from the first memory bank to the second memory bank, the second memory bank having a throughput less than the first memory bank.
18. 18. The method of claim 15, the method further comprising: determining a number of times a flag of the first memory bank is set within a predetermined period of time, the flag indicating an access status of the first memory bank, and The data access rate of the data stored in the first memory bank is determined based on the number of times the flag is set.
19. 19. A computing device, the computing device comprising: a plurality of memory banks; means for storing data in the plurality of memory banks; Means for identifying a data access pattern of the data stored in the plurality of memory banks, and Means for adjusting throughput of one or more of the plurality of memory banks based on the data access pattern of the data such that two or more of the plurality of memory banks have different throughputs.
20. 20. The computer device of claim 19, the computer device further comprising: Means for setting a first memory bank of the plurality of memory banks to a first clock frequency corresponding to a first throughput, and Means for setting a second memory bank of the plurality of memory banks to a second clock frequency corresponding to a second throughput different from the first throughput.

Description

Adaptive memory frequency control and method for computing devices Technical Field The techniques discussed below relate generally to adaptive control of throughput of memory, and in particular, double Data Rate (DDR) memory. Background Double Data Rate (DDR) memory is a type of computer memory commonly used in modern computers, laptops, servers, tablet computers, wearable devices, mobile devices, cellular phones, and the like. It may provide higher data transfer rates than previous generation products of DDR memories, such as Single Data Rate (SDR) memories. DDR memories achieve this increased data transfer rate by transferring data on both the rising and falling edges of the clock signal, effectively doubling the data transfer rate at a given clock frequency. DDR memory is typically specified by a particular generation or version (such as DDR2, DDR3, DDR4, and DDR 5). Each generation has a different maximum clock speed (e.g., megahertz (MHz)) that determines its data transmission rate or throughput. Newer generation DDR memories typically support higher clock speeds and, therefore, faster data transfer rates. DDR memory has specific voltage and clock speed specifications and associated voltage levels. Lower voltage DDR memories tend to be more powerful. In addition, DDR memory may operate at various clock speeds. DDR memories with higher clock speeds may provide better performance in terms of data transfer rates than DDR memories running at lower clock speeds, but higher clock speeds generally consume more power. Disclosure of Invention The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an extensive overview of all contemplated implementations, and is intended to neither identify key or critical elements of all implementations nor delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a one-form as a prelude to the more detailed description that is presented later. Aspects of the present disclosure relate to techniques and apparatus for implementing adaptive frequency control of memory banks in computing devices. The frequency of the memory banks may be independently controlled based on the data access patterns of the memory banks to optimize performance and power consumption of the memory banks. In some aspects, a computing device may save energy by reducing the frequency of one or more memory banks storing infrequently accessed data while maintaining high performance of one or more memory banks for frequently accessed data. One aspect of the present disclosure provides a computing device that includes a plurality of memory banks and one or more processors connected to the plurality of memory banks. The one or more processors are configured to store data in a plurality of memory banks, identify a data access pattern of the data stored in the plurality of memory banks, and adjust a throughput of one or more of the plurality of memory banks based on the data access pattern of the data such that two or more of the plurality of memory banks have different throughputs. Another aspect of the present disclosure provides a method of operating a computing device. The method stores data in a plurality of memory banks of the device. The method identifies a data access pattern of data stored in a plurality of memory banks. The method adjusts throughput of one or more of the plurality of memory banks based on a data access pattern of the data such that two or more of the plurality of memory banks have different throughputs. Another aspect of the present disclosure provides a computing device. The apparatus includes a plurality of memory banks. The apparatus also includes means for storing the data in a plurality of memory banks. The apparatus also includes means for identifying a data access pattern of data stored in the plurality of memory banks. The apparatus also includes means for adjusting a throughput of one or more of the plurality of memory banks based on the data access pattern of the data such that two or more of the plurality of memory banks have different throughputs. To the accomplishment of the foregoing and related ends, one or more embodiments comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more implementations. These aspects are indicative, however, of but a few of the various ways in which the principles of various implementations may be employed and the described implementations are intended to include all such aspects and their equivalents. Drawings Fig. 1 is a block diagram illustrating a computing device employing one or more processors in accordance with some aspects of the present disclosure. FIG. 2 is a block diagram illustrating an exemplary hardware i