CN-122003663-A - Selective switching suppression in multiplexed data paths

Abstract

Techniques are disclosed that relate to selective handoff suppression in multiplexed data paths. Embodiments of the apparatus include a memory circuit and a control circuit. The storage circuitry is configured to store a set of previous selection values that are sent as a set of previous selection signals to a multiplexer within a data path of the computing device. The control circuit is configured to determine whether to maintain the set of previous selection signals or to provide the set of updated selection signals to the multiplexer based at least in part on the set of previous selection signals and the set of input switch likelihood signals. In yet another embodiment, the control circuit is further configured to determine whether a value of a particular input switch likelihood signal corresponding to a previously selected data input of the multiplexer indicates that the previously selected data input is designated as likely to receive a data value change.

Inventors

• E. R. Lissus
• A. Chowdhury
• C. R. Van Bentem

Assignees

• 苹果公司

Dates

Publication Date

20260508

Application Date

20240917

Priority Date

20240808

Claims (20)

1. 1. An apparatus, the apparatus comprising: A first storage circuit configured to store a first set of previous selection values sent as a first set of previous selection signals to a first multiplexer within a data path of a computing device, and The first control circuit is configured to control the first control circuit, the first control circuit is configured to: receiving the first set of previous selection signals and the first set of input switch likelihood signals, and Based at least in part on the first set of previous select signals and the first set of input switch likelihood signals, it is determined whether to maintain the first set of previous select signals or to provide the first set of updated select signals to the first multiplexer.
2. 2. The apparatus of claim 1, wherein: the first set of input switch likelihood signals includes a particular input switch likelihood signal corresponding to a previously selected data input of the first multiplexer; The previously selected data input being a data input selected by applying the first set of previously selected signals, and To determine whether to maintain the previous selection signal or to provide the updated first set of selection signals, the first control circuit is further configured to determine whether the value of the particular input switch likelihood signal indicates that the previously selected data input is designated as likely to receive a data value change.
3. 3. The apparatus of claim 2, wherein the first control circuit is further configured to, during periods for which the first multiplexer is not used to transmit valid data: Providing a signal to the first storage circuit such that the first set of previous selection signals is maintained in response to determining that the value of the particular input switch likelihood signal does not indicate that the previously selected data input is designated as likely to receive a change in data value, and In response to determining that the value of the particular input switch likelihood signal indicates that the previously selected data input is designated as likely to receive a data value change, a signal is provided to the first storage circuit such that the first set of updated selection signals is provided to the first multiplexer.
4. 4. The apparatus of claim 1, wherein the first control circuit is further configured to: receiving a first set of input select signals corresponding to the first multiplexer, and Determining whether the first set of input select signals is configured for communicating data through the first multiplexer.
5. 5. The apparatus of claim 4, wherein the first control circuit is further configured to: generating a first output switching likelihood signal using the first set of input selection signals, the first set of previous selection signals, and the first set of input switching likelihood signals; providing the first output switching likelihood signal to the first memory circuit, and Forwarding the first output switch likelihood signal to an additional control circuit configured to receive an additional set of previous selection signals sent to additional multiplexers within the data path, wherein the first output switch likelihood signal is in the additional set of input switch likelihood signals received by the additional control circuit.
6. 6. The apparatus of claim 1, the apparatus further comprising: a second storage circuit configured to store a second set of previous selection values transmitted as a second set of previous selection signals for a second multiplexer within the data path, wherein a data output of the first multiplexer is connected as one of a set of data inputs of the second multiplexer, and A second control circuit is provided for controlling the first control circuit, the second control circuit is configured to: Receiving the second set of previous selection signals and a second set of input switch likelihood signals, wherein the second set of input switch likelihood signals includes output switch likelihood signals generated by the first control circuit, and Based at least in part on the second set of previous selection signals and the second set of input switch likelihood signals, it is determined whether to maintain the second set of previous selection signals or to provide a second set of updated selection signals to the second multiplexer.
7. 7. A method, the method comprising: Receiving, by a control circuit for a multiplexer and for a first period, a first set of input selection signals for the multiplexer, a first set of previous selection signals sent to the multiplexer during a period immediately preceding the first period, and a first set of input switching likelihood signals, wherein the first set of input selection signals is not configured to pass data through the multiplexer, and Determining, by the control circuit and based on the first set of previous selection signals and the first set of input switch likelihood signals, whether to maintain assertion of the first set of previous selection signals or to provide the first set of updated selection signals to the multiplexer.
8. 8. The method of claim 7, wherein: the first set of input switch likelihood signals includes a particular input switch likelihood signal corresponding to a previously selected data input of the multiplexer; the previously selected data input is an input selected by applying the first set of previously selected signals to the multiplexer, and Determining whether to maintain assertion of the first set of previous selection signals or to provide an updated set of selection signals includes determining whether a value of the particular input switch likelihood signal indicates that the previously selected data input is designated as likely to receive a data value change.
9. 9. The method of claim 8, wherein the value of the particular input switch likelihood signal does not indicate that the previously selected data input is designated as likely to receive a data value change, and further comprising maintaining, by the control circuit, assertion of the first set of previously selected signals for the multiplexer.
10. 10. The method of claim 8, wherein the value of the particular input switch likelihood signal indicates that the previously selected data input is designated as likely to receive a data value change, and further comprising providing, by the control circuit, a set of reset select signals as the first set of updated select signals, the set of reset select signals configured to prevent transmission of the data value change through the multiplexer.
11. 11. The method of claim 9, the method further comprising: Receiving, by the control circuit and for a second period, a second set of input select signals for the multiplexer, wherein the second set of input select signals is configured to pass data through the multiplexer, and The second set of input select signals is provided to the multiplexer by the control circuit.
12. 12. The method of claim 7, wherein determining whether to maintain assertion of the first set of previous selection signals or to provide the first set of updated selection signals comprises generating a first output switch likelihood signal using the first set of previous selection signals and the first set of input switch likelihood signals.
13. 13. The method of claim 12, further comprising forwarding the first output switch likelihood signal to an additional control circuit for an additional multiplexer, wherein the first output switch likelihood signal forms one of an additional set of input switch likelihood signals received by the additional control circuit.
14. 14. A non-transitory computer readable medium having stored thereon design information specifying at least a portion of a design of a first multiplexer control circuit in a format recognized by a manufacturing system configured to use the design information to manufacture a hardware integrated circuit, the first multiplexer control circuit comprising: A first storage circuit configured to store a first set of previous selection values sent as a first set of previous selection signals to a first multiplexer within a data path of a computing device, and The first control circuit is configured to control the first control circuit, the first control circuit is configured to: Receiving said first set of previous selection signals and said first set of input switch likelihood signals, and Based at least in part on the first set of previous select signals and the first set of input switch likelihood signals, it is determined whether to maintain the first set of previous select signals or to provide the first set of updated select signals to the first multiplexer.
15. 15. The computer-readable medium of claim 14, wherein the design information further specifies at least a portion of a design of the data path including the first multiplexer.
16. 16. The computer-readable medium of claim 14, wherein the design information further specifies at least a portion of a design of the computing device.
17. 17. The computer readable medium of claim 16, wherein the computing device is a graphics processing device.
18. 18. The computer-readable medium of claim 14, wherein: the first set of input switch likelihood signals includes a particular input switch likelihood signal corresponding to a previously selected data input of the first multiplexer; The previously selected data input being a data input selected by applying the first set of previously selected signals, and To determine whether to maintain the previous selection signal or to provide the updated first set of selection signals, the first control circuit is further configured to determine whether the value of the particular input switch likelihood signal indicates that the previously selected data input is designated as likely to receive a data value change.
19. 19. The computer-readable medium of claim 18, wherein the first control circuit is further configured to, during periods for which the first multiplexer is not used to transmit valid data: Providing a signal to the first storage circuit such that the first set of previous selection signals is maintained in response to determining that the value of the particular input switch likelihood signal does not indicate that the previously selected data input is designated as likely to receive a change in data value, and In response to determining that the value of the particular input switch likelihood signal indicates that the previously selected data input is designated as likely to receive a data value change, a signal is provided to the first storage circuit such that the first set of updated selection signals is provided to the first multiplexer.
20. 20. The computer-readable medium of claim 15, wherein the design information further specifies at least a portion of a design of a second multiplexer control circuit, the second multiplexer control circuit comprising: a second storage circuit configured to store a second set of previous selection values transmitted as a second set of previous selection signals for a second multiplexer within the data path, wherein a data output of the first multiplexer is connected as one of a set of data inputs of the second multiplexer, and A second control circuit is provided for controlling the first control circuit, the second control circuit is configured to: Receiving the second set of previous selection signals and a second set of input switch likelihood signals, wherein the second set of input switch likelihood signals includes output switch likelihood signals generated by the first control circuit, and Based at least in part on the second set of previous selection signals and the second set of input switch likelihood signals, it is determined whether to maintain the second set of previous selection signals or to provide a second set of updated selection signals to the second multiplexer.

Description

Selective switching suppression in multiplexed data paths Technical Field The present disclosure relates generally to computer processors, and more particularly to control circuitry for routing data in a processor. Background The data processing circuit may comprise a data network in which data is passed through a plurality of cascaded stages. For example, many processors execute instructions using a Single Instruction Multiple Data (SIMD) architecture or a Single Instruction Multiple Thread (SIMT) architecture, where a given operation is designated as a set of multiple threads for performing operations on potentially different data. The processing of large arrays or images may involve the use of forwarding networks that sequentially select different operands. Such networks typically involve cascaded multiplexers, each multiplexer receiving multiple inputs and selecting one of the inputs to forward to the next stage. Drawings Fig. 1 is a block diagram illustrating example elements of a multiplexer control circuit configured to perform selective switching suppression, according to some embodiments. Fig. 2 is a block diagram illustrating example elements of a multiplexed data path according to some embodiments. Fig. 3 is a block diagram illustrating exemplary elements of a set of interconnect multiplexer control circuits configured to control respective interconnect multiplexers, according to some embodiments. Fig. 4 is a block diagram illustrating example elements of a multiplexer control circuit configured to perform selective switching suppression, according to some embodiments. Fig. 5A is a block diagram illustrating example elements of a multiplexer control circuit configured to perform selective switching suppression, according to some embodiments. Fig. 5B is a block diagram illustrating example elements of a multiplexer control circuit configured to perform selective switching suppression, according to some embodiments. Fig. 6 is a flow chart illustrating an example method related to controlling a multiplexer during periods when the multiplexer is not used to transmit valid data, according to some embodiments. Fig. 7 is a flow chart illustrating an example method related to controlling a multiplexer during periods when the multiplexer is not used to transmit valid data, according to some embodiments. Fig. 8 is a flow chart illustrating an example method related to control of a multiplexer, according to some embodiments. Fig. 9 is a block diagram illustrating example elements of a computing device according to some embodiments. FIG. 10 is a block diagram illustrating an example computing device that may be used in various types of systems, according to some embodiments. Fig. 11 is a block diagram illustrating a computer-readable medium storing circuit design information for a computing device, according to some embodiments. Detailed Description As described above, many processors include a data path with cascaded multiplexers. These networks may start with a number of inputs, each of which is a multi-bit signal. This large number of input connections provides an opportunity for data fluctuations or "switching" of lines that are not connected by data paths at that time in a manner that allows the actual use of data on the lines. Even if such an unused signal at the input does not reach the execution circuit through the entire data path, propagation of the unused signal through even a portion of the data path causes gates within the data path multiplexer to switch, wasting dynamic power. One way to prevent extraneous data changes from propagating through the data path is to "data gate" the multiplexer along the path by, for example, setting the multiplexer control input to a reset value, which may include a value for selecting a known "silence bypass" when a given multiplexer is not being used to pass valid data. Changing the multiplexer control input in this way causes the gates themselves to switch compared to the previous input settings, however, this consumes dynamic power. Thus, suppression of extraneous input switching can waste dynamic power if done without such switching actually occurring. This excessive dynamic power consumption can be significant in large forwarding networks that carry multi-bit values, such as those used in SIMD processors. This disclosure describes techniques for implementing "more intelligent" handover suppression. Implementations of the multiplexer control circuit as disclosed herein determine whether to maintain a previous select signal of the multiplexer or to provide an updated select signal. In one embodiment, the determining includes determining whether a change in data value at a data input of the controlled multiplexer is likely to occur at an output of the multiplexer. This may also be referred to as determining whether a data switch will be "visible" at the output of the multiplexer. In the event that valid data is not communicated through the multiplexer, if such