CN-122003670-A - Memory location mapping and de-mapping

Abstract

Methods of operating memory circuits are disclosed. The memory circuit includes a memory array having a memory portion and a spare portion. The method includes receiving a first write command to a first memory address, wherein the first memory address has a state mapped to a first spare memory address, and wherein the first memory address corresponds to a first memory location in a memory portion and the first spare memory address corresponds to a first spare memory location in a spare portion. The method also includes performing a first write operation by attempting to write first data to a first memory location in response to a first write command, determining whether the first write operation was successful, and unmapping the first memory address from the first spare memory address in response to the first write operation being successful.

Inventors

• Sivananda Shetty
• STEFANO AMATO

Assignees

• 英飞凌科技有限责任公司

Dates

Publication Date

20260508

Application Date

20241017

Priority Date

20231017

Claims (20)

1. 1. A method of operating a memory circuit comprising a memory array having a memory portion and a spare portion, the method comprising: Receiving a first write command to a first memory address, wherein the first memory address has a state mapped to a first spare memory address, and wherein the first memory address corresponds to a first memory location in the memory portion and the first spare memory address corresponds to a first spare memory location in the spare portion; Performing a first write operation by attempting to write first data to the first memory location in response to the first write command; Determining whether the first write operation is successful, and The first memory address is unmapped from the first spare memory address in response to the first write operation being successful.
2. 2. The method of claim 1 wherein the first memory address having a state mapped to the first spare memory address indicates that the first memory location is considered a failed memory bit.
3. 3. The method of claim 1, after the first spare memory address is unmapped from the first memory address, the method further comprising: a second memory address is mapped to the first spare memory address, wherein a second memory location associated with the second memory address is considered a failed bit.
4. 4. The method of claim 1, wherein de-mapping the first memory address from the first spare memory address comprises de-associating the first memory address from the first spare memory address in a lookup table.
5. 5. The method of claim 1, further comprising: Performing a second write operation by attempting to write second data to the first memory location in the event that the first memory address does not have a state mapped to a spare memory address, and In response to determining that the second data was not successfully written to the first memory location: mapping the first memory address to a second spare memory address, wherein the second spare memory address is not mapped to any memory address, and The second data is written to a second spare memory location in the spare portion, the second spare memory location corresponding to the second spare memory address.
6. 6. The method of claim 5, wherein the first spare memory location is the same as the second spare memory location.
7. 7. The method of claim 5, wherein mapping the first memory address to the second spare memory address comprises associating the first memory address with the second spare memory address in a lookup table.
8. 8. The method of claim 1, further comprising reading data for the first memory address from the first spare memory location prior to performing the first write operation.
9. 9. The method of claim 1, wherein determining whether the first write operation was successful further comprises: at least one verify read operation is performed to verify whether the first data was successfully written to the first memory location.
10. 10. The method of claim 1, wherein the memory portion is physically separated from the spare portion in the memory array.
11. 11. A memory circuit, comprising: a memory array including a memory portion and a spare portion, and A controller configured to: Performing a first write operation by attempting to write first data to a first memory location in the memory portion, wherein a first memory address corresponds to the first memory location, and when the first write operation is performed, the first memory address has a state mapped to a first spare memory address corresponding to a first spare memory location in the spare portion, and The first memory address is unmapped from the first spare memory address in response to determining that the first data was successfully written to the first memory location during the first write operation.
12. 12. The memory circuit of claim 11, wherein the memory portion of the memory array and the spare portion of the memory array comprise Resistive Random Access Memory (RRAM) cells.
13. 13. The memory circuit of claim 11, wherein the controller is configured to de-map the first memory address from the first spare memory address by de-associating the first memory address from the first spare memory address in a lookup table.
14. 14. The memory circuit of claim 11, wherein the controller is configured to: Performing a second write operation by attempting to write second data to the first memory location in the event that the first memory address does not have a state mapped to a spare memory address, and In response to determining that the second data was not successfully written to the first memory location: Writing the second data to a second spare memory location in the spare portion, the second spare memory location corresponding to a second spare memory address, and The first memory address is mapped to the second spare memory address.
15. 15. The memory circuit of claim 14, wherein the controller is configured to map the first memory address to the second spare memory address by associating the first memory address with the second spare memory address in a lookup table.
16. 16. The memory circuit of claim 11 wherein the controller is configured to read data for the first memory address from the first spare memory location prior to performing the first write operation.
17. 17. The memory circuit of claim 16, wherein the controller is configured to read data for the first memory address from the first memory location after the first memory address is unmapped from the first spare memory address.
18. 18. A system, comprising: an external circuit configured to generate instructions, and A memory circuit configured to receive the instruction from the external circuit, the memory circuit comprising: a memory array including a memory portion and a spare portion, an A controller configured to, in response to a first instruction from the external circuit: Performing a first write operation by attempting to write first data to a first memory location in the memory portion, wherein a first memory address corresponds to the first memory location, and when the first write operation is performed, the first memory address has a state mapped to a first spare memory address corresponding to a first spare memory location in the spare portion, and The first memory address is unmapped from the first spare memory address in response to determining that the first data was successfully written to the first memory location during the first write operation.
19. 19. The system of claim 18, wherein the controller is configured to de-map the first memory address from the first spare memory address by de-associating the first memory address from the first spare memory address in a lookup table.
20. 20. The system of claim 18, wherein the controller is configured to: in response to a second instruction from the external circuit: Performing a second write operation by attempting to write second data to the first memory location in the event that the first memory address does not have a state mapped to a spare memory address, and In response to determining that the second data was not successfully written to the first memory location: mapping the first memory address to a second spare memory address, and The second data is written to a second spare memory location in the spare portion, the second spare memory location corresponding to the second spare memory address.

Description

Memory location mapping and de-mapping Cross Reference to Related Applications The present application is the international application No. 18/380,828 of U.S. non-provisional application filed on day 10 and 17 of 2023, the contents of which are incorporated herein by reference. Technical Field The present invention relates generally to electronic systems and methods, and in particular embodiments, to systems and methods for repairing and freeing memory locations in a memory array. Background Programmable memories are useful in many applications. There are many different types of programmable memory including, but not limited to, resistive Random Access Memory (RRAM), magnetoresistive Random Access Memory (MRAM), phase Change Memory (PCM), ferroelectric random access memory (FERAM), programmable Read Only Memory (PROM), electrically erasable ROM (EEPROM), and flash memory. In order to improve the reliability of the programmable memory, a spare memory area is sometimes included in addition to the main memory array area. If a particular memory cell location of the main memory array region is found to be faulty, that particular memory cell location may be mapped or, in the example, remapped to a location in the spare memory region. In a subsequent write or read operation, data will be written to or read from the mapped spare memory location. Memory cell locations that are considered to be faulty will not be used again to store data. Current technology requires a large amount of spare memory area to meet reliability requirements and is therefore expensive. Disclosure of Invention An aspect of an embodiment is a method of operating a memory circuit that includes a memory array having a memory portion and a spare portion. The method includes receiving a first write command to a first memory address, wherein the first memory address has a state mapped to a first spare memory address, and wherein the first memory address corresponds to a first memory location in a memory portion and the first spare memory address corresponds to a first spare memory location in a spare portion. The method also includes performing a first write operation by attempting to write first data to a first memory location in response to a first write command, determining whether the first write operation was successful, and unmapping the first memory address from the first spare memory address in response to the first write operation being successful. Another aspect of an embodiment is a memory circuit that includes a memory array including a memory portion and a spare portion, and a controller configured to perform a first write operation by attempting to write first data to a first memory location in the memory portion, wherein a first memory address corresponds to the first memory location and, when the first write operation is performed, has a state mapped to a first spare memory address corresponding to the first spare memory location in the spare portion, and to demap the first memory address from the first spare memory address in response to determining that the first data was successfully written to the first memory location during the first write operation. Yet another aspect of an embodiment is a system comprising an external circuit configured to generate an instruction and a memory circuit configured to receive an instruction from the external circuit, the memory circuit comprising a memory array comprising a memory portion and a spare portion, and a controller configured to perform a first write operation by attempting to write first data to a first memory location in the memory portion in response to a first instruction from the external circuit, wherein the first memory address corresponds to the first memory location and, upon performing the first write operation, the first memory address has a state mapped to a first spare memory address corresponding to the first spare memory location in the spare portion, and to demap the first memory address from the first spare memory address in response to determining that the first data was successfully written to the first memory location during the first write operation. Drawings For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: FIG. 1 illustrates a block diagram of an embodiment of a memory system, according to some embodiments of the invention; fig. 2A and 2B illustrate a graphical conceptualization process of a method performed on a portion of a memory according to some embodiments of the invention. FIG. 3 illustrates a graphical conceptualization process of a method according to some embodiments of the invention; FIG. 4 illustrates a flow chart of a method of using memory in accordance with some embodiments of the invention, an Fig. 5 illustrates a flow chart of a method of using memory according to some embodiments of the inventi