CN-122003839-A - Parallel direct feedback decision feedback equalizer for high-speed low-voltage wired links

Abstract

A method for equalizing a data signal includes providing a data signal to a pair of input transistors providing an output signal, using a first decision feedback circuit to contribute a first current or voltage to the output signal, the first current or voltage having a magnitude determined by a first weighted feedback signal, the first decision feedback circuit including a first pull-up circuit coupled to a drain of the first input transistor and a first pull-down circuit coupled to a drain of the first input transistor, and using a second decision feedback circuit to contribute a second current or voltage to the output signal, the second current or voltage having a magnitude determined by a second weighted feedback signal, the second decision feedback circuit including a second pull-up circuit coupled between a drain of the second input transistor and a first voltage rail and a second pull-down circuit coupled between a drain of the second input transistor and a second voltage rail.

Inventors

• D. Valerie
• P sakany Ann.

Assignees

• 高通股份有限公司

Dates

Publication Date

20260508

Application Date

20241002

Priority Date

20231016

Claims (20)

1. 1. A decision feedback equalizer, the decision feedback equalizer comprising: a pair of input transistors configured to receive a differential data signal and further configured to provide an output signal; A first decision feedback circuit, the first decision feedback circuit comprising: a first pull-up circuit coupled between the drain of the first input transistor and a first voltage rail and configured to contribute a first current or voltage to the output signal, the first current or voltage having a magnitude determined by the feedback signal and a first weighting signal, and A first pull-down circuit coupled between the drain of the first input transistor and a second voltage rail and configured to contribute a second current or voltage to the output signal, the second current or voltage having a magnitude determined by the feedback signal and a second weighting signal, and A second decision feedback circuit, the second decision feedback circuit comprising: A second pull-up circuit coupled between the drain of the second input transistor and the first voltage rail and configured to contribute a third current or voltage to the output signal, the third current or voltage having a magnitude determined by the feedback signal and a third weighting signal, and A second pull-down circuit coupled between the drain of the second input transistor and a second voltage rail and configured to contribute a fourth current or voltage to the output signal, the fourth current or voltage having a magnitude determined by the feedback signal and a fourth weighting signal.
2. 2. The decision feedback equalizer of claim 1, wherein the first pull-up circuit and the second pull-down circuit are enabled when the feedback signal is in a first signaling state, and wherein the first pull-down circuit and the second pull-up circuit are enabled when the feedback signal is in a second signaling state.
3. 3. The decision feedback equalizer of claim 1, wherein the first weighted signal is a version of the third weighted signal and the second weighted signal is a version of the fourth weighted signal.
4. 4. The decision feedback equalizer of claim 1, wherein the first, second, third, and fourth weighted signals are calibrated during a system initialization or training process.
5. 5. The decision feedback equalizer of claim 1, wherein the first, second, third, or fourth weighted signals are analog signals.
6. 6. The decision feedback equalizer of claim 1, wherein the first, second, third, or fourth weighted signals are multi-bit digital signals.
7. 7. The decision feedback equalizer of claim 1, further comprising: One or more additional decision feedback circuits connected in parallel with the first decision feedback circuit, each additional decision feedback circuit having: An additional pull-up circuit coupled between the drain of the first input transistor and the first voltage rail and configured to contribute an additional current or voltage to the output signal, the additional current or voltage having a magnitude determined by the feedback signal and a first additional weighting signal, an An additional pull-down circuit coupled between the drain of the first input transistor and the second voltage rail and configured to contribute an additional current or voltage to the output signal, the additional current or voltage having a magnitude determined by the feedback signal and a second additional weighting signal.
8. 8. The decision feedback equalizer of claim 1, further comprising: A latch circuit configured to output a first decoded data bit by capturing a signaling state of the output signal during a first transmission interval.
9. 9. The decision feedback equalizer of claim 8 wherein the feedback signal represents second decoded data bits captured during a second transmission interval preceding the first transmission interval.
10. 10. A decision feedback system, the decision feedback system comprising: A first decision feedback equalizer configured to receive a data signal and provide a first output signal representative of first data bits captured from the data signal, and A second decision feedback equalizer configured to receive the data signal and to provide a second output signal representing a second data bit captured from the data signal using weighted feedback received from the first decision feedback equalizer, Wherein the first decision feedback equalizer comprises: A pair of input transistors configured to receive the data signal and drive the first output signal; A first decision feedback circuit, the first decision feedback circuit comprising: A first pull-up circuit coupled between the drain of the first input transistor and a first voltage rail and configured to contribute a first current or voltage to the first output signal, the first current or voltage having a magnitude determined by a first feedback signal and a first weighting signal, and A first pull-down circuit coupled between the drain of the first input transistor and a second voltage rail and configured to contribute a second current or voltage to the output signal, the second current or voltage having a magnitude determined by the first feedback signal and a second weighting signal, and A second decision feedback circuit, the second decision feedback circuit comprising: A second pull-up circuit coupled between the drain of the second input transistor and the first voltage rail and configured to contribute a third current or voltage to the second output signal, the third current or voltage having a magnitude determined by a second feedback signal and a third weighting signal, and A second pull-down circuit coupled between the drain of the second input transistor and a second voltage rail and configured to contribute a fourth current or voltage to the second output signal, the fourth current or voltage having a magnitude determined by the second feedback signal and a fourth weighting signal.
11. 11. The decision feedback system of claim 10, wherein the first pull-up circuit and the second pull-down circuit are enabled when the first feedback signal is in a first signaling state, and wherein the first pull-down circuit and the second pull-up circuit are enabled when the first feedback signal is in a second signaling state.
12. 12. The decision feedback system of claim 10, wherein the first weighted signal is a version of the third weighted signal and the second weighted signal is a version of the fourth weighted signal.
13. 13. The decision feedback system of claim 10, wherein the first, second, third, and fourth weighted signals are calibrated during a system initialization or training process.
14. 14. The decision feedback system of claim 10, wherein the first weighted signal, the second weighted signal, the third weighted signal, or the fourth weighted signal is an analog signal.
15. 15. The decision feedback system of claim 10, wherein the first weighted signal, the second weighted signal, the third weighted signal, or the fourth weighted signal is a multi-bit digital signal.
16. 16. The decision feedback system of claim 10, further comprising: One or more additional decision feedback circuits connected in parallel with the first decision feedback circuit, each additional decision feedback circuit having: An additional pull-up circuit coupled between the drain of the first input transistor and the first voltage rail and configured to contribute an additional current or voltage to the first output signal, the additional current or voltage having a magnitude determined by the first feedback signal and a fifth weighting signal, an An additional pull-down circuit coupled between the drain of the first input transistor and the second voltage rail and configured to contribute an additional current or voltage to the first output signal, the additional current or voltage having a magnitude determined by the first feedback signal and a sixth weighting signal.
17. 17. The decision feedback system of claim 10, further comprising: a latch circuit configured to capture the first output signal during a first transmission interval, wherein the latch circuit provides the second feedback signal.
18. 18. The decision feedback system of claim 10, wherein the first decision feedback equalizer receives a differential signal representative of the second output signal, wherein the differential signal comprises complementary signals provided to the first and second decision feedback circuits as the first and second feedback signals, respectively.
19. 19. A method for equalizing a data signal, the method comprising: providing a differential data signal to a pair of input transistors configured to provide an equalized output signal; Contributing a first current or voltage to the equalized output signal using a first decision feedback circuit, the first current or voltage having a magnitude determined by a feedback signal and one or more weighting signals, the first decision feedback circuit comprising a first pull-up circuit coupled between a drain of a first input transistor and a first voltage rail and a first pull-down circuit coupled between the drain of the first input transistor and a second voltage rail, and A second decision feedback circuit is used to contribute a second current or voltage to the equalized output signal, the second current or voltage having a magnitude determined by the feedback signal and the one or more weighted signals, the second decision feedback circuit comprising a second pull-up circuit coupled between a drain of a second input transistor and the first voltage rail and a second pull-down circuit coupled between the drain of the second input transistor and a second voltage rail.
20. 20. The method of claim 19, wherein the first pull-up circuit and the second pull-down circuit are enabled when the feedback signal is in a first signaling state, and wherein the first pull-down circuit and the second pull-up circuit are enabled when the feedback signal is in a second signaling state.

Description

Parallel direct feedback decision feedback equalizer for high-speed low-voltage wired links Cross Reference to Related Applications This patent application claims priority from pending U.S. non-provisional application serial No. 18/487,474, filed on 10/16 at 2023, which is assigned to the assignee of the present application and is hereby expressly incorporated by reference as if fully set forth below and for all applicable purposes. Technical Field The present disclosure relates generally to equalization circuitry in a receiving device, and more particularly to decision feedback equalizers for parallel hybrid feedback. Background Electronic device technology has seen explosive growth over the past few years. For example, better communications, hardware, larger networks, and more reliable protocols have driven the development of cellular and wireless communication technologies. Wireless service providers are now able to offer a range of ever expanding features and services to their customers and offer users unprecedented levels of access to information, resources, and communications. To keep pace with these service enhancements, mobile electronic devices (e.g., cellular telephones, tablet computers, laptop computers, etc.) have become more powerful and complex than ever before. A wireless device may include a high-speed bus interface for signal communication between hardware components. For example, the high-speed bus interface may be implemented using a peripheral component interconnect (PCIe) bus. High frequency signals communicated using a bus interface may experience attenuation. Thus, an amplifier and equalizer at the receiver may be used to equalize and then amplify signals received via the bus interface for processing. Disclosure of Invention Certain aspects of the present disclosure relate to systems, devices, methods, and techniques for equalizing a data signal. The differential data signal may be transmitted to the receiver over a communication channel. The receiver may include one or more decision feedback equalizers that provide parallel mixing of feedback. In various aspects of the disclosure, a decision feedback equalizer includes a pair of input transistors configured to receive a differential data signal and configured to provide an output signal, a first decision feedback circuit, and a second decision feedback circuit. The first decision feedback circuit includes a first pull-up circuit coupled between the drain of the first input transistor and a first voltage rail and configured to contribute a first current or voltage to the output signal, the first current or voltage having a magnitude determined by the feedback signal and a first weighting signal, and a first pull-down circuit coupled between the drain of the first input transistor and a second voltage rail and configured to contribute a second current or voltage to the output signal, the second current or voltage having a magnitude determined by the feedback signal and a second weighting signal. The second decision feedback circuit includes a second pull-up circuit coupled between the drain of the second input transistor and the first voltage rail and configured to contribute a third current or voltage to the output signal, the third current or voltage having a magnitude determined by the feedback signal and a third weighting signal, and a second pull-down circuit coupled between the drain of the second input transistor and the second voltage rail and configured to contribute a fourth current or voltage to the output signal, the fourth current or voltage having a magnitude determined by the feedback signal and a fourth weighting signal. In various aspects of the disclosure, a decision feedback system includes a first decision feedback equalizer configured to receive a data signal and provide a first output signal representative of first data bits captured from the data signal, and a second decision feedback equalizer configured to receive the data signal and provide a second output signal representative of second data bits captured from the data signal using weighted feedback received from the first decision feedback equalizer. The first decision feedback equalizer includes a pair of input transistors configured to receive a data signal and drive a first output signal. The first decision feedback equalizer further includes a first decision feedback circuit having a first pull-up circuit coupled between the drain of the first input transistor and the first voltage rail and configured to contribute a first current or voltage to the first output signal, the first current or voltage having a magnitude determined by the first feedback signal and the first weighting signal, and a first pull-down circuit coupled between the drain of the first input transistor and the second voltage rail and configured to contribute a second current or voltage to the output signal, the second current or voltage having a magnitude determined by the first feedb