CN-122003959-A - Memory array, manufacturing method thereof, memory and electronic equipment

CN122003959ACN 122003959 ACN122003959 ACN 122003959ACN-122003959-A

Abstract

The embodiment of the application provides a memory array, a manufacturing method thereof, a memory and electronic equipment, relates to the technical field of semiconductor memory, and aims to reduce the size of the memory under the condition that the capacity of the memory is not affected. The memory array includes a substrate, a transistor chain, a capacitor array, and an electrical connection structure. The transistor chain includes a plurality of transistors connected in series. In the capacitor array, a vertical projection of a columnar capacitor on a transistor chain overlaps with a first pole or a second pole of a transistor. The transistor chain and the columnar capacitor electrically connected with the transistor chain form a chain type storage architecture. The electrodes of two adjacent columnar capacitors electrically connected with the same transistor chain are respectively and electrically connected with two ends of the electric connection structure, so that the two adjacent columnar capacitors are connected in series through the electric connection structure. The electrical connection structure does not occupy the space between two adjacent columnar capacitors, so that the space between two adjacent columnar capacitors is the same or approximately the same as the space between the first pole and the second pole of the transistor.

Inventors

GU JUNXING
LV HANGBING
XU YANNAN
WANG CHAO
ZHAO WEIJIE
WANG XIAO
SU DIQING
LI SHAORUI
DU KAI

Assignees

华为技术有限公司

Dates

Publication Date: 20260508
Application Date: 20231215

Claims (20)

A memory array, comprising: A substrate; At least two transistor chains, at least one part of the transistor chains is arranged in the substrate, the transistor chains comprise a plurality of transistors connected in series, and the first pole or the second pole of two adjacent transistors are shared in the same transistor chain so that the two adjacent transistors are connected in series; The array of capacitors is arranged on one side of the transistor chain away from the substrate in a stacking way, and comprises a plurality of columnar capacitors, wherein the vertical projection of one columnar capacitor on the transistor chain is at least partially overlapped with a first pole or a second pole of one transistor; At least one electric connection structure, range upon range of set up in one side that the electric capacity array deviates from the transistor chain, same two adjacent electrode of columnar electric capacity that transistor chain electricity is connected, respectively with electric connection structure's both ends electricity is connected, so that two adjacent columnar electric capacity passes through electric connection structure establishes ties.
The memory array of claim 1, wherein, The columnar capacitor includes: A first columnar electrode, one end facing the transistor chain is electrically connected with a first pole or a second pole of the transistor; a second columnar electrode, at least a portion of which is disposed within the first columnar electrode; A dielectric layer at least a portion of which is disposed within the first columnar electrode, and the dielectric layer is located between the first columnar electrode and the second columnar electrode; Two adjacent columnar capacitors electrically connected with the same transistor chain are respectively a first columnar capacitor and a second columnar capacitor, and two ends of the electric connection structure are respectively electrically connected with the second columnar electrode of the first columnar capacitor and the first columnar electrode of the second columnar capacitor.
The memory array of claim 2, wherein, The memory array further comprises a first insulating layer, wherein the first insulating layer covers the capacitor array; the electrical connection structure includes: The first end of the first via hole is electrically connected with the second cylindrical electrode of the first cylindrical capacitor; the second conducting hole penetrates through the first insulating layer, and the first end of the second conducting hole is electrically connected with the first columnar electrode of the second columnar capacitor; The first conducting part is arranged on one side, deviating from the capacitor array, of the first insulating layer, and two ends of the first conducting part are respectively and electrically connected with the second end of the first conducting hole and the second end of the second conducting hole.
The memory array of claim 2, wherein in any one of the first columnar capacitor and the second columnar capacitor, the second columnar electrode protrudes from the first columnar electrode toward one end of the electrical connection structure; the memory array further comprises a first insulating layer, wherein the first insulating layer covers the capacitor array; the electrical connection structure includes: the first end of the third via hole is electrically connected with the first columnar electrode of the second columnar capacitor; the second conducting part is arranged on one side, away from the capacitor array, of the first insulating layer, and two ends of the second conducting part are respectively electrically connected with one end, facing the electric connection structure, of the second cylindrical electrode of the first cylindrical capacitor and the second end of the third conducting hole.
The memory array of claim 4, wherein the memory array is configured to store a plurality of data, The memory array further includes: The second insulating layer is arranged on one side of the transistor chain, which is away from the substrate, and the capacitor array is embedded in the second insulating layer; The electric connection column is arranged in the second insulating layer and is positioned at one side of the third through hole away from the second through hole, and the electric connection column is electrically connected with the side wall of the first columnar electrode and the third through hole.
The memory array of claim 2, wherein, The columnar capacitor includes: A first columnar electrode; a second columnar electrode, at least a portion of which is disposed within the first columnar electrode; A dielectric layer at least a portion of which is disposed within the first columnar electrode, and the dielectric layer is located between the first and second columnar electrodes; The transistor comprises a transistor chain, a first columnar capacitor, a second columnar capacitor, a first columnar electrode, a second columnar electrode, a first electrode and a second electrode, wherein the two adjacent columnar capacitors which are electrically connected with the same transistor chain are respectively a first columnar capacitor and a second columnar capacitor; the second columnar electrode of the first columnar capacitor penetrates through the integral structural member and is electrically connected with the second pole of the transistor; A first blind hole is formed in one side, away from the transistor chain, of the integrated structural member, and a second cylindrical electrode of the second cylindrical capacitor is positioned in the first blind hole; The at least one electric connection structure comprises a first electric connection structure, and in the adjacent integrated structural member, a second cylindrical electrode of the second cylindrical capacitor and a second cylindrical electrode of the first cylindrical capacitor are respectively and electrically connected with two ends of the first electric connection structure.
The memory array of claim 6, wherein the memory array is configured to store a plurality of data, The memory array further comprises a first insulating layer, wherein the first insulating layer covers the capacitor array; Adjacent the integrative structure is first integrative structure and second integrative structure respectively, first electric connection structure includes: A fourth via hole penetrating the first insulating layer, wherein a first end of the fourth via hole is electrically connected with a second cylindrical electrode of the second cylindrical capacitor in the first integral structural member; A fifth via hole penetrating through the first insulating layer, wherein a first end of the fifth via hole is electrically connected with a second cylindrical electrode of the first cylindrical capacitor in the second integral structural member; And the third conducting part is arranged on one side, away from the capacitor array, of the first insulating layer, and two ends of the third conducting part are respectively and electrically connected with the second end of the fourth conducting hole and the second end of the fifth conducting hole.
The memory array of claim 6, wherein the memory array is configured to store a plurality of data, In the columnar capacitor, one end of the second columnar electrode, which is away from the transistor chain, extends out of the first columnar electrode; The capacitor array comprises a plurality of integral structural members, two ends of the first electric connection structure are respectively and electrically connected with one ends of two adjacent second cylindrical electrodes, which are located in different integral structural members and deviate from the transistor chain.
The memory array according to any one of claims 6 to 8, wherein, In the transistor chain, the columnar capacitor electrically connected with the transistor at the tail end or the head end is a third columnar capacitor; A second blind hole is formed in one side, away from the transistor chain, of the third columnar capacitor, and a second columnar electrode of the third columnar capacitor is positioned in the second blind hole; The at least one electric connection structure further comprises a second electric connection structure, wherein the second cylindrical electrode of the third cylindrical capacitor and the second cylindrical electrode of the adjacent first cylindrical capacitor or second cylindrical capacitor are respectively and electrically connected with two ends of the second electric connection structure.
The memory array of any of claims 2-9, wherein the dielectric layer comprises a ferroelectric thin film layer or a resistive layer.
The memory array according to any one of claims 1 to 10, wherein, The first pole or the second pole of the transistor is positioned in the vertical projection range of the columnar capacitor on the transistor chain.
The memory array of any one of claims 1-11, wherein the first and second poles of the transistor are disposed within the substrate, the memory array further comprising: The first electrode wire is electrically connected with the grid electrode of the transistor, is arranged on the surface of one side of the substrate facing the capacitor array, or is arranged in the substrate.
The memory array of claim 12, wherein the memory array further comprises: a second electrode line, a first end of one of the transistor chains being electrically connected to one of the second electrode lines; and a third electrode line electrically connected to second ends of the at least two transistor chains.
The memory array of any one of claims 1-13 wherein, The memory array further includes: And the contact part is arranged between the transistor chain and the capacitor array, and one contact part is electrically connected with one electrode of the columnar capacitor and one first electrode or second electrode of the transistor.
The memory array of any one of claims 1-14 wherein, The columnar capacitors electrically connected with the at least two transistor chains are arranged in a matrix; Or alternatively And the columnar capacitors electrically connected with the at least two transistor chains are arranged in a honeycomb mode.
A memory, comprising: the memory array of any one of claims 1-15; and the controller is electrically connected with the storage array and is used for controlling the reading and writing of the storage array.
An electronic device, comprising: A circuit board; The memory of claim 16, the circuit board being electrically connected to the memory.
A method of fabricating a memory array, comprising: Forming at least a portion of a plurality of transistors within a substrate, a first pole or a second pole of two adjacent ones of the transistors being common such that the two adjacent ones of the transistors are connected in series to form a transistor chain; Forming a plurality of columnar capacitors, wherein the vertical projection of one columnar capacitor on the transistor chain is at least partially overlapped with a first pole or a second pole of one transistor; electrically connecting two electrodes of one of the columnar capacitors with a first pole and a second pole of one of the transistors, respectively, to form a memory cell; And two ends of the electric connection structure are respectively and electrically connected with electrodes of two adjacent columnar capacitors electrically connected with the same transistor chain, so that the two adjacent columnar capacitors are connected in series through the electric connection structure.
The method of claim 18, wherein the memory array is fabricated by, Forming any one of the plurality of columnar capacitances includes: forming a first columnar electrode; forming a dielectric layer within the first columnar electrode; Forming a second columnar electrode within the dielectric layer, the dielectric layer being located between the first columnar electrode and the second columnar electrode; Two adjacent columnar capacitors electrically connected with the same transistor chain are respectively a first columnar capacitor and a second columnar capacitor, and the forming of the electric connection structure comprises the following steps: And two ends of the electric connection structure are respectively and electrically connected with the second columnar electrode of the first columnar capacitor and the first columnar electrode of the second columnar capacitor.
The method of claim 18, wherein the memory array is fabricated by, Two adjacent columnar capacitors electrically connected with the same transistor chain are respectively a first columnar capacitor and a second columnar capacitor, and forming the first columnar capacitor and the second columnar capacitor comprises the following steps: Forming a first columnar electrode of the first columnar capacitor and a first columnar electrode of the second columnar capacitor, and connecting the first columnar electrode of the first columnar capacitor and the first columnar electrode of the second columnar capacitor into an integral structural member; Electrically connecting an end of the integral structure facing the transistor chain with a first pole of the transistor; Manufacturing a through hole penetrating through the integral structural member on the integral structural member, forming a second cylindrical electrode of the first cylindrical capacitor in the through hole, and electrically connecting the second cylindrical electrode with the second electrode of the transistor; forming a first blind hole at one side of the integral structural member, which is far away from the transistor chain, and forming a second cylindrical electrode of the second cylindrical capacitor in the first blind hole; Forming at least one electric connection structure comprises forming a first electric connection structure on one side of the plurality of columnar capacitors, which is away from the transistor chain, and respectively connecting two ends of the first electric connection structure with the adjacent integrated structural members, wherein the second columnar electrode of the second columnar capacitor is electrically connected with the second columnar electrode of the first columnar capacitor.

Description

Memory array, manufacturing method thereof, memory and electronic equipment Technical Field The present application relates to the field of semiconductor memory technologies, and in particular, to a memory array, a manufacturing method thereof, a memory, and an electronic device. Background Along with the continuous improvement of the requirements of users on the diversification of functions of electronic devices, the information processing capacity of the electronic devices is increased, so that the memories in the electronic devices are required to have larger storage capacity. The memory cells of the memory, such as a dynamic random access memory (dynamic random access memory, DRAM), may include transistors and capacitors for storing information. The capacity of the capacitor needs to meet certain requirements to be able to match the information processing requirements of the electronic device. However, in general, the capacitance of the capacitor is proportional to the size of the capacitor, and after the capacitance of the capacitor is increased, the size of the capacitor is also increased, so that the requirement of the integration level of the electronic device cannot be met. Disclosure of Invention The application provides a memory array, a manufacturing method thereof, a memory and electronic equipment, which are used for reducing the size of the memory without affecting the capacity of the memory. In order to achieve the above purpose, the application adopts the following technical scheme: In one aspect of the application, a memory array is provided that includes a substrate, a transistor chain, a capacitor array, and at least one electrical connection structure. Wherein at least a portion of at least two transistor chains are disposed within the substrate, the transistor chains including a plurality of transistors connected in series. In the same transistor chain, the first pole or the second pole of two adjacent transistors are shared, so that the two adjacent transistors are connected in series. The capacitor array layer is arranged on one side, away from the substrate, of the transistor chain, and comprises a plurality of columnar capacitors. A vertical projection of a columnar capacitance onto the transistor chain at least partially overlaps with the first pole or the second pole of a transistor. In addition, two electrodes of one columnar capacitor are electrically connected to a first electrode and a second electrode of one transistor, respectively, to form a memory cell. On the basis, at least one electric connection structure is arranged on one side of the capacitor array, which is far away from the transistor chain, and electrodes of two adjacent columnar capacitors electrically connected with the same transistor chain are respectively and electrically connected with two ends of the electric connection structure, so that the two adjacent columnar capacitors are connected in series through the electric connection structure. In summary, the first pole or the second pole of two adjacent transistors are shared, and a plurality of transistors can be connected in series to form the transistor chain. In addition, two electrodes of the columnar capacitor are respectively and electrically connected with the first pole and the second pole of the same transistor, so that one transistor and one columnar capacitor electrically connected with the first pole and the second pole of the transistor form one memory unit. In this case, the transistor chain and the pillar capacitor to which the transistor chain is electrically connected may constitute a chain-type memory architecture. The chained memory architecture is more compact in memory cell layout than the 1T1C (one transistor and one capacitor) structure adopted by the conventional DRAM, and is beneficial to reducing the size of a memory array and a memory with the memory array. In addition, compared with the plane capacitor, the columnar capacitor occupies smaller area than the plane capacitor under the condition that the capacitance is the same in the same horizontal plane (such as the bearing surface of the substrate of the storage capacitor), so that the size of the storage unit is reduced under the condition that the memory capacity is not influenced, and the size of the storage array and the memory with the storage array can be reduced. On this basis, the vertical projection of a columnar capacitance on the transistor chain at least partially overlaps with the first pole or the second pole of a transistor. And in the chained memory architecture, the electric connection structure for connecting two adjacent columnar capacitors in series is arranged on one side of the capacitor array, which is away from the transistor chain, so that the electric connection structure can be prevented from occupying the space between the two adjacent columnar capacitors, and the space between the two adjacent columnar capacitors can be the same or approximately the