CN-122003960-A - Memory device and method of manufacturing the same

Abstract

A memory device, a memory system, and a method of manufacturing are provided. The disclosed memory device includes an array of vertical transistors arranged in a lateral plane, each vertical transistor including a channel structure extending vertically with respect to the lateral plane, and a drain structure including a first semiconductor layer in contact with a first end of the channel structure and having a first dopant concentration and a first lattice structure, and a second semiconductor layer between the first semiconductor layer and a bit line and having a second dopant concentration different from the first dopant concentration and a second lattice structure different from the first lattice structure.

Inventors

• Ai Yiming
• ZHANG HE
• ZHENG YUHUAN
• YU CHENGXING
• DENG DAN

Assignees

• 长江存储科技有限责任公司

Dates

Publication Date

20260508

Application Date

20240903

Claims (20)

1. 1. A storage device, comprising: An array of vertical transistors, the array of vertical transistors arranged in a lateral plane, each vertical transistor comprising: A channel structure extending perpendicularly with respect to the transverse plane, and A drain structure, the drain structure comprising: a first semiconductor layer in contact with a first end of the channel structure and having a first dopant concentration and a first lattice structure, an A second semiconductor layer located between the first semiconductor layer and the bit line and having a second dopant concentration different from the first dopant concentration and a second lattice structure different from the first lattice structure.
2. 2. The memory device of claim 1, wherein the second dopant concentration is at least 1000 times the first dopant concentration.
3. 3. The storage device of claim 1, wherein: the first semiconductor layer is a monocrystalline silicon layer, and The second semiconductor layer is a polysilicon layer.
4. 4. The storage device of claim 3, wherein: the polysilicon layer has a dopant concentration gradient that increases from a first side in contact with the first semiconductor layer to a second side in contact with the bit line.
5. 5. The storage device of claim 3, wherein: the polysilicon layer includes a uniform second dopant concentration along a vertical direction.
6. 6. The storage device of claim 4, further comprising: A polysilicon seed layer located between the single crystal silicon layer and the polysilicon layer.
7. 7. The storage device of claim 1, wherein: the gate structures of each row of vertical transistors in the first lateral direction are connected to each other to form a word line.
8. 8. The storage device of claim 7, wherein: the second semiconductor layer of the drain structure of each column of vertical transistors along a second lateral direction is connected to the same bit line.
9. 9. The storage device of claim 7, further comprising: and a partition wall extending along the first transverse direction, wherein the partition wall is positioned between the channel structures of two adjacent rows of vertical transistors.
10. 10. The memory device of claim 1, wherein each vertical transistor further comprises: a source structure in contact with a second end of the channel structure, the second end being opposite the first end.
11. 11. The storage device of claim 10, further comprising: An array of capacitors coupled to the source structures of the array of vertical transistors.
12. 12. The storage device of claim 11, wherein: The first electrode of each capacitor being coupled to the source structure of the corresponding vertical structure through a source node contact, and The second electrodes of the array of capacitors are connected to each other to form a common electrode.
13. 13. A method of forming a memory device, comprising: forming an array of vertical transistors, comprising: forming an array of semiconductor bodies arranged in a lateral plane, each semiconductor body extending perpendicularly relative to the lateral plane; lightly doping the first end of the semiconductor substrate to form a first semiconductor layer; Removing a portion of the lightly doped first end of the semiconductor body to form a trench, and A heavily doped second semiconductor layer is formed in the trench, wherein a first lattice structure of the semiconductor body is different from a second lattice structure of the heavily doped second semiconductor layer.
14. 14. The method of claim 13, wherein forming the array of semiconductor bodies comprises: forming a partition wall along a first transverse direction to separate the semiconductor substrates of adjacent rows, and Spacers are formed in the second lateral direction to separate adjacent columns of semiconductor bodies, Wherein the first ends of the semiconductor bodies in each column of semiconductor bodies are connected to each other and the trenches are formed between adjacent spacer layers.
15. 15. The method of claim 13, wherein forming a heavily doped second semiconductor layer comprises doping the second semiconductor layer such that a second dopant concentration of the second semiconductor layer is at least 1000 times a first dopant concentration of the first semiconductor layer.
16. 16. The method of claim 15, wherein, Forming the first semiconductor layer includes forming a monocrystalline silicon layer, and Forming the second semiconductor layer includes forming a polysilicon layer.
17. 17. The method of claim 16, wherein forming the heavily doped second semiconductor layer comprises depositing a plurality of polysilicon sublayers to form a dopant concentration gradient along a vertical direction.
18. 18. The method of claim 16, wherein forming the heavily doped second semiconductor layer comprises: Depositing the polysilicon layer in the trench, and The polysilicon layer is doped with phosphorus to form a uniform second dopant concentration in a vertical direction.
19. 19. The method of claim 16, wherein forming the heavily doped second semiconductor layer comprises: forming a seed polysilicon layer on the monocrystalline silicon layer, and The polysilicon layer is epitaxially grown from the seed polysilicon layer to form a dopant concentration gradient in a vertical direction.
20. 20. The method of claim 14, wherein forming the array of vertical transistors further comprises: Forming gate structures, each gate structure on a lateral side of a corresponding semiconductor body, Wherein the gate structures of each row of vertical transistors along the first lateral direction are connected to each other to form a word line.

Description

Memory device and method of manufacturing the same Technical Field The present disclosure relates generally to the field of semiconductor technology, and more particularly, to memory devices and methods of manufacturing the same. Background Planar memory cells can be scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of the memory cell approaches the lower limit, planar processing and fabrication techniques become challenging and costly. As a result, the storage density for the planar memory cell approaches the upper limit. A three-dimensional (3D) memory architecture may address density limitations in planar memory cells. The 3D memory architecture includes a memory array and peripheral circuitry for facilitating operation of the memory array. Disclosure of Invention One aspect of the present disclosure provides a memory device including an array of vertical transistors arranged in a lateral plane, each vertical transistor including a channel structure extending vertically with respect to the lateral plane, and a drain structure including a first semiconductor layer in contact with a first end of the channel structure and having a first dopant concentration and a first lattice structure, and a second semiconductor layer between the first semiconductor layer and a bit line and having a second dopant concentration different from the first dopant concentration and a second lattice structure different from the first lattice structure. In some embodiments, the second dopant concentration is at least 1000 times the first dopant concentration. In some embodiments, the first semiconductor layer is a monocrystalline silicon layer and the second semiconductor layer is a polycrystalline silicon layer. In some embodiments, the polysilicon layer has a dopant concentration gradient that increases from a first side in contact with the first semiconductor layer to a second side in contact with the bit line. In some embodiments, the polysilicon layer includes a uniform second dopant concentration along the vertical direction. In some embodiments, the memory device further includes a polysilicon seed layer between the single crystal silicon layer and the polysilicon layer. In some implementations, the gate structures of each row of vertical transistors along the first lateral direction are connected to each other to form a word line. In some embodiments, the second semiconductor layer of each column of vertical transistors along a second lateral direction is connected to the same bit line. In some embodiments, the memory device further includes a spacer wall extending in the first lateral direction between the channel structures of two adjacent rows of vertical transistors. In some embodiments, each vertical transistor further includes a source structure in contact with a second end of the channel structure, wherein the second end is opposite the first end. In some embodiments, the memory device further includes an array of capacitors coupled to the source structures of the array of vertical transistors. In some embodiments, a first electrode of each capacitor is coupled with the source structure of the corresponding vertical structure through a source node contact, and a second electrode of the array of capacitors is connected to each other to form a common electrode. Another aspect of the present disclosure provides a method of forming a memory device including forming an array of vertical transistors including forming an array of semiconductor bodies arranged in a lateral plane, each semiconductor body extending vertically with respect to the lateral plane, lightly doping a first end of the semiconductor body to form a first semiconductor layer, removing a portion of the lightly doped first end of the semiconductor body to form a trench, and forming a heavily doped second semiconductor layer in the trench, wherein a first lattice structure of the semiconductor body is different from a second lattice structure of the heavily doped second semiconductor. In some embodiments, forming the array of semiconductor bodies includes forming a spacer wall in a first lateral direction to separate adjacent rows of semiconductor bodies and forming a spacer layer in a second lateral direction to separate adjacent columns of semiconductor bodies, wherein the first ends of the semiconductor bodies of each column of semiconductor bodies are connected to each other and the trench is formed between adjacent spacer layers. In some embodiments, forming the heavily doped second semiconductor layer includes doping the second semiconductor layer such that a second dopant concentration of the second semiconductor layer is at least 1000 times a first dopant concentration of the first semiconductor layer. In some embodiments, forming the first semiconductor layer includes forming a monocrystalline silicon layer and forming the second semiconductor