CN-122003962-A - Semiconductor structure and manufacturing method thereof

Abstract

The semiconductor structure includes a first semiconductor chip and a second semiconductor chip stacked with the first semiconductor chip along a first direction. The first semiconductor chip includes a first memory structure including a first contact structure extending along a first direction and a first peripheral structure disposed on a first substrate, the first peripheral structure being in contact with the first memory structure and including a second contact structure extending along the first direction. The second semiconductor chip is bonded to the first semiconductor chip by a chip-to-chip bonding layer, and the first contact structure and the second contact structure are coupled by a first coupling layer.

Inventors

• ZHAO DAI
• XIAO LIANG
• MIAO LINA
• ZHOU WENBIN
• HUO ZONGLIANG

Assignees

• 长江存储控股股份有限公司

Dates

Publication Date

20260508

Application Date

20240902

Claims (20)

1. 1. A semiconductor structure, comprising: a first semiconductor chip, the first semiconductor chip comprising: A first storage structure including a first contact structure extending along a first direction, and A first peripheral structure disposed on the first substrate, the first peripheral structure being in contact with the first memory structure and including a second contact structure extending along the first direction, and A second semiconductor chip stacked with the first semiconductor chip along the first direction, Wherein the second semiconductor chip is bonded to the first semiconductor chip through a chip-to-chip bonding layer, and The first contact structure and the second contact structure are coupled by a first coupling layer.
2. 2. The semiconductor structure of claim 1, wherein the second semiconductor chip comprises: a second storage structure including a third contact structure extending along the first direction, and A second peripheral structure disposed on a second substrate, the second peripheral structure being in contact with the second storage structure and including a fourth contact structure extending along the first direction.
3. 3. The semiconductor structure of claim 2, wherein the third contact structure and the fourth contact structure are coupled by a second coupling layer.
4. 4. The semiconductor structure of claim 3, wherein the chip-to-chip bonding layer comprises a first mixed dielectric-to-dielectric and metal-to-metal bonding layer.
5. 5. The semiconductor structure of claim 4, wherein the first mixed dielectric-to-dielectric and metal-to-metal bonding layer comprises a first nitrogen doped silicon carbide layer and a first metal structure.
6. 6. The semiconductor structure of claim 5, wherein the second contact structure and the third contact structure are coupled through the first metal structure and the first metal structure penetrates the first nitrogen-doped silicon carbide layer.
7. 7. The semiconductor structure of claim 2, wherein the second memory structure of the second semiconductor chip is bonded to the first peripheral structure of the first semiconductor chip.
8. 8. The semiconductor structure of claim 7, wherein the first and second memory structures are separated by the first peripheral structure.
9. 9. The semiconductor structure of claim 7, wherein the second contact structure penetrates the first substrate and the fourth contact structure penetrates the second substrate.
10. 10. The semiconductor structure of claim 1, wherein the first coupling layer comprises a second mixed dielectric-to-dielectric and metal-to-metal bonding layer.
11. 11. The semiconductor structure of claim 10, wherein the first contact structure and the second contact structure are contacted by a second metal structure in the second hybrid dielectric-to-dielectric and metal-to-metal bonding layer.
12. 12. The semiconductor structure of claim 3, wherein the second coupling layer comprises a third hybrid dielectric-to-dielectric and metal-to-metal bonding layer.
13. 13. The semiconductor structure of claim 12, wherein the third contact structure and the fourth contact structure are contacted by a third metal structure in the third hybrid dielectric-to-dielectric and metal-to-metal bonding layer.
14. 14. The semiconductor structure of claim 2, further comprising: A logic die disposed below the second semiconductor chip and configured to control the semiconductor structure.
15. 15. The semiconductor structure of claim 14, wherein the logic die comprises a fifth contact structure extending along the first direction and the logic die is bonded to the second semiconductor chip through a fourth hybrid dielectric-to-dielectric and metal-to-metal bonding layer.
16. 16. The semiconductor structure of claim 15, wherein the fifth contact structure is in contact with the fourth contact structure through the fourth hybrid dielectric-to-dielectric and metal-to-metal bonding layer.
17. 17. The semiconductor structure of claim 16, further comprising: A bond pad disposed below the logic die in contact with the fifth contact structure.
18. 18. A semiconductor structure, comprising: a first semiconductor chip, the first semiconductor chip comprising: A first memory structure including a first vertical transistor extending in a first direction and a first memory element in contact with the first vertical transistor, and A first peripheral structure disposed on the first substrate, the first peripheral structure being in contact with the first memory structure, and A second semiconductor chip stacked with the first semiconductor chip along the first direction, the second semiconductor chip including: A second memory structure including a second vertical transistor extending in the first direction and a second memory element in contact with the second vertical transistor, and A second peripheral structure disposed on a second substrate, the second peripheral structure being in contact with the second storage structure, Wherein the second semiconductor chip is bonded to the first semiconductor chip by a first hybrid dielectric-to-dielectric and metal-to-metal bonding layer.
19. 19. The semiconductor structure of claim 18, wherein the first hybrid dielectric-to-dielectric and metal-to-metal bonding layer comprises a first carbon-doped silicon nitride layer and a first metal structure.
20. 20. The semiconductor structure of claim 18, wherein the first storage structure comprises a first contact structure extending along the first direction, the first peripheral structure comprises a second contact structure extending along the first direction, and the first contact structure and the second contact structure are coupled by a first coupling layer.

Description

Semiconductor structure and manufacturing method thereof Technical Field The present disclosure relates to semiconductor structures and methods of fabricating the same, and more particularly to memory devices, memory systems, and methods of fabricating the same. Background Planar memory cells are scaled to smaller dimensions by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of the memory cell approaches the lower limit, planar processing and fabrication techniques become challenging and expensive. As a result, the storage density of the planar memory cell approaches the upper limit. The high bandwidth memory (high bandwidth memory, HBM) uses stacked memory devices or memory chips to achieve efficient data movement and access. While using less power in smaller form factors, HBM devices may achieve higher bandwidths. HBM devices have been applied to high performance graphics accelerators, networking equipment, high performance data centers, artificial intelligence (ARTIFICIAL INTELLIGENCE, AI) and machine learning (MACHINE LEARNING, ML) training, and various supercomputers. Disclosure of Invention In accordance with one aspect of the present disclosure, a semiconductor structure is disclosed. The semiconductor structure includes a first semiconductor chip and a second semiconductor chip stacked with the first semiconductor chip along a first direction. The first semiconductor chip includes a first memory structure including a first contact structure extending along a first direction and a first peripheral structure disposed on a first substrate, the first peripheral structure being in contact with the first memory structure and including a second contact structure extending along the first direction. The second semiconductor chip is bonded to the first semiconductor chip by a chip-to-chip bonding layer, and the first contact structure and the second contact structure are coupled by a first coupling layer. In some embodiments, the second semiconductor chip includes a second memory structure including a third contact structure extending along the first direction and a second peripheral structure disposed on a second substrate, the second peripheral structure being in contact with the second memory structure and including a fourth contact structure extending along the first direction. In some embodiments, the third contact structure and the fourth contact structure are coupled by a second coupling layer. In some embodiments, the chip-to-chip bonding layer includes a first mixed dielectric-to-dielectric and metal-to-metal bonding layer (first hybrid dielectric-to-DIELECTRIC AND METAL-to-metal bonding layer). In some embodiments, the first mixed dielectric-to-dielectric and metal-to-metal bonding layer includes a first nitrogen doped silicon carbide layer and a first metal structure. In some embodiments, the second contact structure and the third contact structure are coupled by the first metal structure, and the first metal structure penetrates the first nitrogen doped silicon carbide layer. In some implementations, the second memory structure of the second semiconductor chip is bonded to the first peripheral structure of the first semiconductor chip. In some embodiments, the first storage structure and the second storage structure are separated by the first peripheral structure. In some embodiments, the second contact structure penetrates the first substrate and the fourth contact structure penetrates the second substrate. In some embodiments, the first coupling layer includes a second mixed dielectric-to-dielectric and metal-to-metal bonding layer. In some embodiments, the first contact structure and the second contact structure are contacted by a second metal structure in the second mixed dielectric-to-dielectric and metal-to-metal bonding layer. In some embodiments, the second coupling layer includes a third mixed dielectric-to-dielectric and metal-to-metal bonding layer. In some embodiments, the third contact structure and the fourth contact structure are contacted by a third metal structure in the third hybrid dielectric-to-dielectric and metal-to-metal bonding layer. In some embodiments, the semiconductor structure further includes a logic die disposed below the second semiconductor chip, the logic die configured to control the semiconductor structure. In some embodiments, the logic die includes a fifth contact structure extending along the first direction, and the logic die is bonded to the second semiconductor chip through a fourth hybrid dielectric-to-dielectric and metal-to-metal bonding layer. In some embodiments, the fifth contact structure is in contact with the fourth contact structure through the fourth hybrid dielectric-to-dielectric and metal-to-metal bonding layer. In some embodiments, the semiconductor structure further includes a bond pad disposed below the logic die in contact with the fifth contact structure. I