CN-122003963-A - Memory device and manufacturing method thereof

Abstract

A memory device includes a first semiconductor chip, a second semiconductor chip, a first contact structure, and a second contact structure. The first semiconductor chip includes a first semiconductor structure and a first dielectric layer penetrating the first semiconductor structure. The second semiconductor chip is stacked with the first semiconductor chip in a first direction, and the second semiconductor chip includes a second semiconductor structure and a second dielectric layer penetrating the second semiconductor structure. The first contact structure extends in the first dielectric layer along the first direction and is in contact with a first metal layer of the first semiconductor chip. The second contact structure extends in the first direction in the first dielectric layer and the second dielectric layer and is in contact with a second metal layer of the second semiconductor chip. The first dielectric layer and the second dielectric layer are aligned in the first direction.

Inventors

• MIAO LINA
• XIAO LIANG
• XIAO WENJING
• ZHOU WENBIN
• HUO ZONGLIANG

Assignees

• 长江存储控股股份有限公司

Dates

Publication Date

20260508

Application Date

20240902

Claims (20)

1. 1. A memory device, comprising: A first semiconductor chip including a first semiconductor structure and a first dielectric layer penetrating the first semiconductor structure; a second semiconductor chip stacked with the first semiconductor chip in a first direction, the second semiconductor chip including a second semiconductor structure and a second dielectric layer penetrating the second semiconductor structure; A first contact structure extending in the first dielectric layer along the first direction and contacting a first metal layer of the first semiconductor chip, and A second contact structure extending in the first direction in the first dielectric layer and the second dielectric layer and contacting a second metal layer of the second semiconductor chip, Wherein the first dielectric layer and the second dielectric layer are aligned in the first direction.
2. 2. The memory device of claim 1, wherein the first semiconductor chip further comprises a first dielectric bonding layer, the second semiconductor chip further comprises a second dielectric bonding layer, and the first semiconductor chip and the second semiconductor chip are bonded through the first dielectric bonding layer and the second dielectric bonding layer.
3. 3. The memory device of claim 1, wherein the first semiconductor structure comprises a first memory structure and a first peripheral structure stacked in the first direction.
4. 4. The memory device of claim 3, wherein the first memory structure is bonded to the first peripheral structure by a hybrid bonding layer.
5. 5. The memory device of claim 4, wherein the hybrid bonding layer comprises a dielectric bonding layer and a conductive bonding structure.
6. 6. The memory device of claim 1, wherein the first metal layer and the second metal layer extend in a second direction perpendicular to the first direction.
7. 7. The memory device of claim 6, wherein the first contact structure and the second contact structure are arranged side-by-side along the second direction.
8. 8. The memory device of claim 7, wherein a length of the second contact structure in the first direction is greater than a length of the first contact structure in the first direction.
9. 9. The memory device of claim 7, wherein a first end of the first contact structure and a first end of the second contact structure are coplanar in the second direction, a second end of the first contact structure is in contact with the first metal layer, and a second end of the second contact structure is in contact with the second metal layer.
10. 10. The memory device of claim 1, wherein the first semiconductor structure comprises a first substrate and the first dielectric layer penetrates the first substrate in the first direction.
11. 11. The memory device of claim 1, wherein the first contact structure comprises a first conductive layer extending in the first direction and a first adhesive layer covering the first conductive layer.
12. 12. A system, comprising: An interposer; a memory device disposed on the interposer, comprising: A first semiconductor chip including a first semiconductor structure and a first dielectric layer penetrating the first semiconductor structure; a second semiconductor chip stacked with the first semiconductor chip in a first direction, the second semiconductor chip including a second semiconductor structure and a second dielectric layer penetrating the second semiconductor structure; A first contact structure extending in the first dielectric layer along the first direction and contacting a first metal layer of the first semiconductor chip, and A second contact structure extending in the first direction in the first dielectric layer and the second dielectric layer and contacting a second metal layer of the second semiconductor chip, Wherein the first dielectric layer and the second dielectric layer are aligned in the first direction; a base die disposed between the interposer and the memory device configured to control the memory device, and And a compute die disposed on the interposer, wherein the base die and the compute die are integrated on the interposer along a second direction perpendicular to the first direction.
13. 13. The system of claim 12, wherein the base die includes control circuitry to control the memory device through the first contact structure and the second contact structure.
14. 14. The system of claim 12, wherein the base die and the compute die are bonded to a same surface of the interposer.
15. 15. The system of claim 12, wherein the base die is bonded to the memory device through a hybrid bonding layer.
16. 16. The system of claim 15, wherein the hybrid bonding layer comprises a dielectric bonding layer and a conductive bonding structure.
17. 17. A method of forming a memory device, comprising: Forming a first semiconductor chip including a first memory structure and a first peripheral structure on a first substrate, and a first dielectric structure penetrating the first substrate; Forming a second semiconductor chip including a second memory structure and a second peripheral structure on a second substrate, and a second dielectric structure penetrating the second substrate; bonding the first semiconductor chip and the second semiconductor chip in a first direction, and A first contact structure is formed penetrating the first dielectric structure and a second contact structure is formed penetrating the first dielectric structure and the second dielectric structure.
18. 18. The method of claim 17, further comprising: Bonding the first semiconductor chip and the second semiconductor chip to a base die, and The base die and the compute die are bonded to an interposer.
19. 19. The method of claim 17, wherein forming the first semiconductor chip further comprises forming a first landing layer under the first dielectric structure, and wherein forming the second semiconductor chip further comprises forming a second landing layer under the second dielectric structure.
20. 20. The method of claim 19, wherein forming the first semiconductor chip comprises: Forming the first dielectric structure on a first side of the first substrate; forming the first peripheral structure on the first side of the first substrate; Forming the first memory structure on a third substrate; Bonding the first peripheral structure and the first memory structure, and A thinning operation is performed on a second side of the first substrate opposite the first side to expose the first dielectric structure.

Description

Memory device and manufacturing method thereof Background The present disclosure relates to semiconductor devices and methods of making the same, and in particular to memory devices, memory systems, and methods of making the same. Planar memory cells are scaled to smaller dimensions by improving process technology, circuit design, programming algorithms, and fabrication processes. However, as the feature size of the memory cells approaches the lower limit, planar processing and fabrication techniques become challenging and expensive. Thus, the memory density of the planar memory cell approaches the upper limit. High Bandwidth Memory (HBM) uses stacked memory devices or memory chips to achieve efficient data movement and access. While using less power in smaller form factors, HBM devices may achieve higher bandwidths. HBM devices have been applied to high performance graphics accelerators, networking devices, high performance data centers, artificial Intelligence (AI) and Machine Learning (ML) training, and various supercomputers. Disclosure of Invention According to one aspect of the present disclosure, a memory device is disclosed. The memory device includes a first semiconductor chip, a second semiconductor chip, a first contact structure, and a second contact structure. The first semiconductor chip includes a first semiconductor structure and a first dielectric layer penetrating the first semiconductor structure. The second semiconductor chip is stacked with the first semiconductor chip in the first direction, and the second semiconductor chip includes a second semiconductor structure and a second dielectric layer penetrating the second semiconductor structure. The first contact structure extends in a first direction in the first dielectric layer and is in contact with the first metal layer of the first semiconductor chip. The second contact structure extends in the first direction in the first dielectric layer and the second dielectric layer and is in contact with the second metal layer of the second semiconductor chip. The first dielectric layer and the second dielectric layer are aligned in a first direction. In some embodiments, the first semiconductor chip further includes a first dielectric bonding layer, the second semiconductor chip further includes a second dielectric bonding layer, and the first semiconductor chip and the second semiconductor chip are bonded through the first dielectric bonding layer and the second dielectric bonding layer. In some implementations, the first semiconductor structure includes a first memory structure and a first peripheral structure stacked in a first direction. In some implementations, the first memory structure is bonded to the first peripheral structure through a hybrid bonding layer. In some embodiments, the hybrid bonding layer includes a dielectric bonding layer and a conductive bonding structure. In some embodiments, the first metal layer and the second metal layer extend in a second direction perpendicular to the first direction. In some embodiments, the first contact structure and the second contact structure are arranged side by side along the second direction. In some embodiments, the length of the second contact structure in the first direction is greater than the length of the first contact structure in the first direction. In some embodiments, the first end of the first contact structure and the first end of the second contact structure are coplanar in the second direction, the second end of the first contact structure is in contact with the first metal layer, and the second end of the second contact structure is in contact with the second metal layer. In some embodiments, the first semiconductor structure includes a first substrate and the first dielectric layer penetrates the first substrate in a first direction. In some embodiments, the first contact structure includes a first conductive layer extending in a first direction and a first adhesive layer covering the first conductive layer. In accordance with another aspect of the present disclosure, a system is disclosed. The system includes an interposer, a memory device disposed on the interposer, a base die disposed between the interposer and the memory device configured to control the memory device, and a compute die disposed on the interposer. The memory device includes a first semiconductor chip, a second semiconductor chip, a first contact structure, and a second contact structure. The first semiconductor chip includes a first semiconductor structure and a first dielectric layer penetrating the first semiconductor structure. The second semiconductor chip is stacked with the first semiconductor chip in the first direction, and the second semiconductor chip includes a second semiconductor structure and a second dielectric layer penetrating the second semiconductor structure. The first contact structure extends in a first direction in the first dielectric layer and is in contact with the first m