CN-122003965-A - Method for manufacturing semiconductor device and plasma processing method

CN122003965ACN 122003965 ACN122003965 ACN 122003965ACN-122003965-A

Abstract

In a GAA FET having a structure in which linear or plate-shaped channels are laminated, in a step of manufacturing work function metals differently depending on the type of transistor, even when a gap is present between laminated channels (3) after a gate insulating film and the work function metal are formed on the channels, the work function metals can be manufactured differently without using a sacrificial layer filling the gap. Therefore, an organic film mask covering the laminated channel is coated, patterning for exposing a necessary transistor region is performed, the organic film mask is vertically etched, and then a protective insulating film (13) is deposited over the entire surface. Next, the protective insulating film (13) is isotropically etched, and the protective insulating film (13) is left only on the side walls of the organic film mask. In this state, only the work function metal of the pattern opening and the organic film mask for removing the gap between the buried channels (3) are removed by the work function metal of the pattern opening. By performing the vertical etching from the organic film mask to the removal of the work function metal by a continuous process using the same apparatus, the process can be simplified.

Inventors

MIURA MAKOTO
SATO KIYOHIKO
HIRABAYASHI EIJI

Assignees

株式会社日立高新技术

Dates

Publication Date: 20260508
Application Date: 20240906

Claims (10)

1. A method for manufacturing a semiconductor device having a semiconductor laminated structure in which a gate region for forming a gate electrode is formed on a semiconductor substrate, a sheet-like semiconductor layer or a linear semiconductor layer having a gate insulating film and a work function controlling metal formed on a surface thereof is laminated in the gate region, The method for manufacturing a semiconductor device is characterized by comprising: A first step of etching an organic film mask formed so as to cover the semiconductor laminated structure and to fill a gap between the laminated semiconductor layers in a direction perpendicular to the semiconductor substrate; a second step of depositing a first insulating film on the exposed area of the work function control metal and the side wall of the organic film mask after the first step; A third step of removing the first insulating film in a region other than a sidewall of the organic film mask by isotropic etching after the second step; a fourth step of removing the work function control metal exposed at a portion other than the gap after the third step; a fifth step of removing the exposed organic film mask after the fourth step, and And a sixth step of removing the work function controlling metal of the gap by isotropic etching after the fifth step.
2. The method for manufacturing a semiconductor device according to claim 1, wherein, The first to sixth steps are performed continuously in the same plasma processing apparatus in which the semiconductor device is formed by plasma processing.
3. The method for manufacturing a semiconductor device according to claim 1, wherein, The first insulating film is a silicon nitride film or a silicon carbonitride film.
4. The method for manufacturing a semiconductor device according to claim 1, wherein, The fourth step is to remove the work function control metal exposed at a portion other than the gap by repeating a cyclic process of isotropic etching and anisotropic etching more than once.
5. The method for manufacturing a semiconductor device according to claim 1, wherein, The fourth and fifth steps are repeated two or more times.
6. The method for manufacturing a semiconductor device according to claim 1, wherein, The first insulating film is a plurality of films different in material.
7. The method for manufacturing a semiconductor device according to claim 6, wherein, The first insulating film is composed of a lower insulating film in contact with the gate insulating film and an upper insulating film formed on the upper side of the lower insulating film, The underlying insulating film is a silicon nitride film or a silicon carbonitride film, The upper insulating film is a silicon oxide film.
8. The method for manufacturing a semiconductor device according to claim 1, wherein, The method for manufacturing a semiconductor device further comprises: a seventh step of forming a second insulating film after the fourth step, and And an eighth step of removing the second insulating film deposited in a region other than the sidewall of the organic film mask by isotropic etching.
9. The method for manufacturing a semiconductor device according to claim 8, wherein, The first insulating film in contact with the gate insulating film is a silicon nitride film or a silicon carbonitride film, The second insulating film is a silicon oxide film.
10. A plasma processing method for performing plasma etching on a work function control metal of a semiconductor laminated structure having a gate region where a gate electrode is formed on a semiconductor substrate, laminating a sheet-like semiconductor layer or a linear semiconductor layer having a gate insulating film and a work function control metal formed on a surface thereof in the gate region, The plasma processing method is characterized by comprising the following steps: A first step of etching an organic film mask formed so as to cover the semiconductor laminated structure and to fill a gap between the laminated semiconductor layers in a direction perpendicular to the semiconductor substrate; a second step of depositing a first insulating film on the exposed area of the work function control metal and the side wall of the organic film mask after the first step; A third step of removing the first insulating film in a region other than a sidewall of the organic film mask by isotropic etching after the second step; a fourth step of removing the work function control metal exposed at a portion other than the gap after the third step; a fifth step of removing the exposed organic film mask after the fourth step, and And a sixth step of removing the work function controlling metal of the gap by isotropic etching after the fifth step.

Description

Method for manufacturing semiconductor device and plasma processing method Technical Field The present disclosure relates to a method of manufacturing a semiconductor device and a plasma processing method. Background In order to continuously improve the functions and performance of integrated circuit chips as semiconductor devices, high integration of transistors as semiconductor elements mounted on integrated circuits is continuously demanded. Up to now, high integration of transistors has been achieved mainly by miniaturization of transistor element dimensions. In order to achieve miniaturization of elements while maintaining or improving transistor performance, many improvements have been made in transistor construction and materials constituting transistors. Examples of such improvements include introduction of strain into a source region and a drain region in a metal oxide semiconductor field effect Transistor (MOSFET: metal Oxide Semiconductor FIELD EFFECT Transistor), introduction of a high dielectric gate insulating film and a metal gate, and a change in channel structure from Planar (Planar) type to Fin (Fin) type Transistor having a three-dimensional structure. With further miniaturization, the channel is a layered body in the form of a line (thin line) or a sheet, and the transistor structure is changed to a full-Around Gate FET (GAA) in which the channel is covered with a Gate. These improvements are introduced for the purpose of suppressing short channel effects caused by the reduction of the transistor size, that is, the phenomenon that a leakage current flows between the source and the drain with a reduced distance even in a state where the transistor is turned off. Among them, the metal gate electrode has a function of suppressing the leakage current by the metal work function, and is characterized by applying an appropriate material according to the use of the transistor (low leakage current or high operation current) or the conductivity type (n-type or p-type). Therefore, the metal gate is also called a work function control metal (work function metal ), and the fabrication of the metal is an indispensable technique for miniaturization of the transistor size depending on the characteristics of the transistor. A method for differently manufacturing the work function metal in a transistor having a Fin-type channel is disclosed in patent document 1, for example. A high dielectric constant (high-k) gate insulating film and a work function metal are sequentially deposited on a trench having a Fin shape, and after a mask material is applied or deposited, patterning parallel to the orientation direction of the trench is performed, and the mask material is etched in a vertical direction. At this time, fin-type channels are divided into channels covered by the mask and channels not covered by the mask. Then, the work function metal deposited on the Fin-type channel of the specific transistor can be removed by isotropically etching the film thickness of the work function metal by an amount corresponding to the film thickness. By repeating the above process using a plurality of mask patterns, a desired work function metal can be deposited on a desired transistor. On the other hand, for example, non-patent document 1 discloses a method for manufacturing the above-mentioned work function metal in GAA transistors. In the GAA transistor, since trenches having a linear or plate-like shape are stacked, gaps between the stacked trenches are buried by the mask material when the mask material is applied or deposited. Therefore, after patterning is performed to etch the mask material in the vertical direction, the mask material remains in the gap between the laminated trenches in the region where the mask material should be etched. Therefore, the work function metal deposited in the region between the laminated trenches is protected by the mask material, and the work function remains in the region between the laminated trenches even when the work function metal is etched by an amount corresponding to the film thickness. Therefore, there is a problem that the work function metal of the transistor region where the work function metal is to be removed cannot be removed. Non-patent document 1 also discloses a method for avoiding some of the above problems. The high-k gate insulating film and the work function metal are sequentially deposited on the trenches having a linear or plate-like shape, and then gaps between the stacked trenches are filled with a sacrificial layer made of an insulating film. Then, by coating or depositing the mask material, a phenomenon in which the mask material enters a gap between channels can be avoided. In this case, however, the sacrificial layer that enters the gap between the stacked channels needs to be removed by isotropic etching. Since the isotropic etching is performed from the side wall of the sacrificial layer buried in the gap, an etching amount of at least half the width of