CN-122003966-A - Transistor device

Abstract

A transistor device is disclosed.

Inventors

• W. Keyndell
• C. Fahman
• F. Heller

Assignees

• 英飞凌科技奥地利有限公司

Dates

Publication Date

20260508

Application Date

20240930

Priority Date

20230929

Claims (17)

1. 1. A transistor device, comprising: Transistor unit (10), and A source electrode (41), Wherein each transistor cell (10) comprises: a source region (11) of a first doping type; A body region (12) of a second doping type complementary to the first doping type and adjoining the source region (11); A gate electrode (21) adjacent to the body region (12), insulated from the body region (12) by a gate dielectric (22), and arranged in a gate trench (120) extending from the first surface (101) of the semiconductor body (100) into the semiconductor body (100); a body contact region (17) adjoining the body region (12) and electrically connected to the source electrode (41), Wherein a distance (d 4) between the body contact region (17) and the gate dielectric (22) is less than 300 nanometers.
2. 2. The transistor device of claim 1 wherein, The distance (d 4) between the body contact region (17) and the gate dielectric is greater than 150 nanometers.
3. 3. The transistor device of claim 1 or 2, wherein the transistor device further comprises: An insulating layer (5) arranged between the source electrode (41) and the first surface (101) of the semiconductor body (100).
4. 4. The transistor device of claim 3 wherein, The body contact region (17) is connected to the source electrode (41) by a conductive via (42), said conductive via (42) extending from the source electrode (41) through the insulating layer (5) and part of the semiconductor body (100) to the body contact region (17).
5. 5. The transistor device of claim 4 wherein, The distance between the conductive via (42) and the gate dielectric (22) is less than 350 nanometers.
6. 6. The transistor device of claim 5 wherein, The source region (11) and the body region (12) of two adjacent transistor cells (10) are arranged in the mesa region between adjacent gate trenches (120), and Each transistor cell (10) of two adjacent transistor cells (10) comprises a respective body contact region (17) and a respective conductive via (42).
7. 7. The transistor device of claim 5 wherein, The source region (11) and the body region (12) of two adjacent transistor cells (10) are arranged in the mesa region between adjacent gate trenches (120), and Two adjacent transistor cells (10) comprise a common body contact region (17) and a common conductive via (42) connected between the body contact region (17) and a source electrode (41).
8. 8. The transistor device of claim 6, wherein the transistor device further comprises: A further body contact region (18) which is arranged between the body contact regions (17) of adjacent transistor cells (10) and which is connected to the source electrode (41) by a further conductive via (43).
9. 9. The transistor device of claim 8 wherein, The further body contact regions (18) are each spaced apart from the body contact regions (17) of adjacent transistor cells (10).
10. 10. The transistor device of claim 8 wherein, The further body contact regions (18) each adjoin a body contact region (17) of an adjacent transistor cell (10).
11. 11. The transistor device according to any of the preceding claims, wherein, The doping concentration of the body contact region (17) is at least 10 times the doping concentration of the body region (17).
12. 12. The transistor device of any preceding claim, wherein the transistor device further comprises: A drift region (14) of the first doping type and a compensation region (15) of the second doping type; a drain region (13) of a first doping type, and A buffer region (16) of a first doping type, which is arranged between the drain region (13) and the drift region (14) and the compensation region (15), Wherein each drift region (14) adjoins the body region (12) of at least one transistor cell (10), and Each compensation region (15) is connected to a source electrode (41) and is adjacent to at least one drift region (14).
13. 13. The transistor device of claim 12 wherein, Each compensation region (15) adjoins the body region (12) of at least one transistor cell (10).
14. 14. The transistor device according to claim 12 or 13, wherein, The dimension (d 6) of the buffer region (16) in the vertical direction (z) of the semiconductor body (100) is less than 27%, less than 25% or less than 20% of the distance between the buffer region (16) and the first surface (101).
15. 15. The transistor device of claim 14 wherein, The distance (d 1) between the buffer zone (16) and the first surface (101) is selected between 35 micrometers and 50 micrometers.
16. 16. A transistor device, comprising: Transistor unit (10), and A source electrode (41), Wherein each transistor cell (10) comprises: a source region (11) of a first doping type; A body region (12) of a second doping type complementary to the first doping type and adjoining the source region (11); A gate electrode (21) adjacent to the body region (12), insulated from the body region (12) by a gate dielectric (22), and arranged in a gate trench (120) extending from the first surface (101) of the semiconductor body (100) into the semiconductor body (100); a body contact region (17) adjoining the body region (12) and electrically connected to the source electrode (41), Wherein the body contact region (17) is connected to the source electrode (41) by means of a conductive via (42), said conductive via (42) extending from the source electrode (41) through the insulating layer (5) and part of the semiconductor body (100) to the body contact region (17), The distance between the conductive via (42) and the gate dielectric (22) is less than 350 nanometers.
17. 17. The transistor device of claim 16, wherein a distance between the conductive via (42) and the gate dielectric (22) is less than 300 nanometers.

Description

Transistor device Technical Field The present disclosure relates generally to a transistor device, and more particularly to a superjunction transistor device. Background The superjunction transistor device may include a plurality of transistor cells, each transistor cell including a gate electrode, a source region, a body region adjacent to the gate electrode and dielectrically insulated from the gate electrode by a gate dielectric, and a drift region adjacent to the body region. In the on-state (conductive state) of the transistor device, a conductive channel is present in the body region along the gate dielectric. In the off state, the conductive channel is interrupted. The source region, the adjoining body region and the drift region form a parasitic bipolar transistor, wherein the body region forms a base of the parasitic transistor. During operation of the transistor device, an operating situation may occur in which charge carriers are injected into the body region, which may cause the parasitic bipolar transistor to conduct, such that the transistor device is in an on-state in an uncontrolled manner at least for a certain period of time. This is highly undesirable. Disclosure of Invention One example relates to a transistor device. The transistor device includes a transistor cell and a source electrode. Each of the transistor cells includes a source region of a first doping type, a body region of a second doping type complementary to the first doping type and adjoining the source region, a gate electrode adjacent the body region, wherein the gate electrode is dielectric insulated from the body region by a gate dielectric and is disposed in a gate trench extending from a first surface of a semiconductor body into the semiconductor body. Furthermore, each transistor cell comprises a body contact region adjoining the body region and electrically connected to the source electrode. The distance between the body contact region and the gate dielectric is less than 300 nanometers. Another example relates to a transistor device. The transistor device includes a transistor cell and a source electrode. Each of the transistor cells includes a source region of a first doping type, a body region of a second doping type complementary to the first doping type and adjoining the source region, a gate electrode adjacent the body region, the gate electrode being dielectric insulated from the body region by a gate dielectric, and disposed in a gate trench extending from a first surface of a semiconductor body into the semiconductor body. Furthermore, each transistor cell comprises a body contact region adjoining the body region and electrically connected to the source electrode. The body contact region is connected to the source electrode by a conductive via extending from the source electrode through the insulating layer and a portion of the semiconductor body to the body contact region. The distance between the conductive via and the gate dielectric is less than 350 nanometers. Drawings Examples are explained below with reference to the drawings. The drawings are intended to illustrate certain principles so that only aspects necessary to understand these principles are shown. The figures are not drawn to scale. In the drawings, like reference numerals refer to like features. Fig. 1 schematically illustrates a vertical cross-section of a portion of a transistor device comprising a plurality of transistor cells; Figures 2 and 3 show horizontal cross-sectional views of the transistor device shown in figure 1 in different horizontal cross-sections; fig. 4 to 7 show detailed views of transistor cells according to different examples; fig. 8A to 8C illustrate one example of a method for forming a contact region and a contact via of a transistor cell; fig. 8A to 9C illustrate another example of a method for forming a contact region and a contact via of a transistor cell; Fig. 10A to 10C illustrate yet another example of a method for forming a contact region and a contact via of a transistor cell, and Fig. 11A to 11B show top views of transistor devices according to different examples. Detailed Description In the following detailed description, reference is made to the accompanying drawings. The accompanying drawings constitute a part of the specification and illustrate examples of how the invention may be used and practiced for purposes of illustration. It is to be understood that features of the various embodiments described herein may be combined with each other, unless specifically indicated otherwise. Fig. 1 schematically illustrates a portion of a transistor device comprising a plurality of transistor cells 10. More specifically, fig. 1 shows a vertical cross-section of a portion of a semiconductor body 100 of a transistor device in which a transistor cell 10 is integrated. The semiconductor body 100 comprises a monocrystalline semiconductor material. For example, the semiconductor material is silicon (Si) or silicon carbi