CN-122003982-A - Bow mitigation in high aspect ratio oxide and nitride etches

Abstract

A method of semiconductor processing may include forming a plasma effluent. The plasma effluent may then contact a carbon-containing hard mask and an oxide cap. The plasma effluents may etch one or more features in the oxide cap through one or more apertures of the carbon-containing hard mask. Etching may create a tapered profile for one or more features in the oxide cap. The one or more features may be characterized by a critical dimension at a bottom of the one or more features. The critical dimension may be less than or about 80% of the width of the one or more slots.

Inventors

• M. A. Algalibu
• S. D. Sherpa
• TAKESHITA KENJI
• A. Lanjian

Assignees

• 应用材料公司

Dates

Publication Date

20260508

Application Date

20241003

Priority Date

20231006

Claims (20)

1. 1.A semiconductor processing method, the semiconductor processing method comprising: forming a plurality of plasma effluents; Contacting a carbon-containing hard mask with an oxide cap in a processing region of a semiconductor processing chamber with the plasma effluent, wherein a substrate is disposed on a substrate support within the processing region, wherein a plurality of alternating material layers cover the substrate, wherein the oxide cap covers the plurality of alternating material layers, and the carbon-containing hard mask covers the oxide cap, wherein the carbon-containing hard mask has one or more slots that allow the plasma effluent to enter the oxide cap, and One or more features partially passing through the oxide cap are etched with the plasma effluent through the one or more apertures of the carbon-containing hard mask to create a tapered profile for the one or more features, the one or more features characterized by a critical dimension at a bottom of the one or more features, wherein the critical dimension is less than or about 80% of a width of the one or more apertures.
2. 2. The semiconductor processing method of claim 1, wherein the critical dimension is less than or about 70% of the width of the one or more slots.
3. 3. The semiconductor processing method of claim 1, wherein the one or more features are characterized by a critical dimension of less than or about 50 nm.
4. 4. The semiconductor processing method of claim 1, wherein the tapered profile of the one or more features is characterized by a taper angle of less than or about 30 degrees.
5. 5. The semiconductor processing method of claim 1, further comprising: Etching the one or more apertures in the carbon-containing hard mask to expose the oxide cap, and One or more recesses in the oxide cap are etched through the one or more gaps, wherein the one or more features are later formed within the one or more recesses.
6. 6. The semiconductor processing method of claim 1, further comprising: The oxide cap and the plurality of alternating material layers are etched using a main etch such that the one or more features extend through both the oxide cap and the plurality of alternating material layers to form one or more channels.
7. 7. The semiconductor processing method of claim 6, wherein the one or more channels define a first stack and a second stack, and wherein a second critical dimension between the first stack and the second stack is less than or about 130% of the critical dimension.
8. 8. The semiconductor processing method of claim 7, wherein the second critical dimension is a maximum distance between the first stack and the second stack.
9. 9. The semiconductor processing method of claim 8, wherein the second critical dimension is less than or about 65 nm.
10. 10. The semiconductor processing method of claim 1, wherein the oxide cap has a thickness of less than or about 100 nm a.
11. 11. The semiconductor processing method of claim 1, wherein the one or more gaps are characterized by a width of less than or about 100nm.
12. 12. The semiconductor processing method of claim 1, wherein carbon-and fluorine-containing precursors are used to form the plasma effluent.
13. 13. The semiconductor processing method of claim 12, wherein the carbon and fluorine containing precursor comprises CF 4 .
14. 14. The semiconductor processing method of claim 1, wherein the plasma effluent generates a plasma power of about 5000W or less.
15. 15. The semiconductor processing method of claim 1, wherein a bias voltage of a power supply of the semiconductor processing chamber is about 5000 volts or less.
16. 16. A semiconductor processing method, the semiconductor processing method comprising: forming a plurality of plasma effluents containing carbon and fluorine precursors; Contacting a carbon-containing hard mask with an oxide cap in a processing region of a semiconductor processing chamber with the plasma effluent, wherein a substrate is disposed on a substrate support within the processing region, wherein a plurality of alternating material layers cover the substrate, wherein the oxide cap covers the plurality of alternating material layers, and the carbon-containing hard mask covers the oxide cap, wherein the carbon-containing hard mask has one or more slots that allow the plasma effluent to enter the oxide cap, and One or more features partially passing through the oxide cap are etched with the plasma effluent through the one or more apertures of the hard mask to create a tapered profile for the one or more features, the one or more features characterized by a critical dimension at a bottom of the one or more features of less than or about 100 nm.
17. 17. The semiconductor processing method of claim 16, further comprising: forming the carbon-containing hard mask overlying the oxide cap; Etching the one or more gaps in the carbon-containing hard mask to expose the oxide cap, wherein the one or more gaps are characterized by a width of less than or about 120 nm, and The oxide cap is partially etched to form the one or more features.
18. 18. A semiconductor processing method, the semiconductor processing method comprising: forming a plurality of plasma effluents containing carbon and fluorine precursors; Contacting a carbon-containing hard mask with an oxide cap in a processing region of a semiconductor processing chamber with the plasma effluent, wherein a substrate is disposed on a substrate support within the processing region, wherein a plurality of alternating material layers cover the substrate, wherein the oxide cap covers the plurality of alternating material layers, and the carbon-containing hard mask covers the oxide cap, wherein the carbon-containing hard mask has one or more slots that allow the plasma effluent to enter the oxide cap; etching one or more features partially through the oxide cap with the plasma effluents through the one or more apertures of the hard mask to create a tapered profile for the one or more features, the one or more features characterized by critical dimensions at a bottom of the one or more features, wherein the tapered profile of the one or more features is characterized by a taper angle of less than or about 20 degrees, and The oxide cap and the plurality of alternating material layers are etched using a main etch such that the one or more features extend through both the oxide cap and the plurality of alternating material layers to form one or more channels.
19. 19. The semiconductor processing method of claim 18, wherein the one or more features are characterized by a critical dimension of a width of the one or more gaps that is less than or about 90%.
20. 20. The semiconductor processing method of claim 18, wherein the one or more channels define a first stack and a second stack, and wherein a second critical dimension between the first stack and the second stack is less than or about 100 nm.

Description

Bow mitigation in high aspect ratio oxide and nitride etches Technical Field The priority benefit of U.S. non-provisional application Ser. No. 18/482,384, entitled "BOW MITIGATION IN HIGH ASPECT RATIO OXIDE AND NITRIDE ETCHES," filed on 6, 10, 2023, is incorporated herein by reference in its entirety for all purposes. The present invention relates to semiconductor systems, processes, and apparatus. More specifically, the present invention relates to etching processes in semiconductor manufacturing. Background Integrated circuits are manufactured by a process that produces a complex layer of patterned material on the surface of a substrate. Creating patterned material on a substrate requires a controlled method for removing the exposed material. Chemical etching is used for various purposes, including transferring a pattern in the photoresist to an underlying layer, thinning the layer, or thinning the lateral dimensions of features already present on the surface. It would be generally desirable to have an etching process that etches one material faster than another material, facilitating, for example, a pattern transfer process. Due to the variety of materials, circuits, and processes, etching processes have been developed with selectivity to various materials. Bowing may occur when etching features with high aspect ratios, such as 3D NAND flash. Significant bowing can result in mechanical and/or structural instability in structures formed using high aspect ratio features. Furthermore, significant bowing can cause critical dimensions between structures to become too wide to meet the specifications of a particular semiconductor design. Similarly, significant bow can cause the final semiconductor element to become nonfunctional, reducing yield during the fabrication process. Accordingly, there is a need for improved systems and methods that can be used to produce high quality devices and structures. These and other needs are met by the present invention. Disclosure of Invention In some embodiments, a semiconductor processing method may include forming a plasma effluent, contacting a carbon-containing hard mask with an oxide cap in a processing region of a semiconductor processing chamber, wherein a substrate is disposed on a substrate support within the processing region, wherein a plurality of alternating material layers cover the substrate, wherein the oxide cap covers the plurality of alternating material layers, and the carbon-containing hard mask covers the oxide cap, wherein the carbon-containing hard mask has one or more slots that allow the plasma effluent to enter the oxide cap, and etching one or more features partially through the oxide cap with the plasma effluent through the one or more slots of the carbon-containing hard mask to create a tapered profile for the one or more features, the one or more features characterized by a critical dimension at a bottom of the one or more features, wherein the critical dimension is less than or about 80% of a width of the one or more slots. In some embodiments, a semiconductor processing method may include forming a plasma effluent of a carbon-and fluorine-containing precursor, contacting a carbon-containing hard mask with an oxide cap in a processing region of a semiconductor processing chamber, wherein a substrate is disposed on a substrate support within the processing region, wherein a plurality of alternating material layers cover the substrate, wherein the oxide cap covers the oxide cap, and the carbon-containing hard mask has one or more apertures that allow the plasma effluent to enter the oxide cap, and etching one or more features partially through the oxide cap with the plasma effluent through the one or more apertures of the hard mask to create a tapered profile for the one or more features, the one or more features characterized by a critical dimension at a bottom of the one or more features that is less than or about 100 nm. In some embodiments, a semiconductor processing method may include forming a plasma effluent of a carbon-and fluorine-containing precursor, contacting a carbon-containing hard mask with an oxide cap in a processing region of a semiconductor processing chamber, wherein a substrate is disposed on a substrate support within the processing region, wherein a plurality of alternating material layers cover the substrate, wherein the oxide cap covers the plurality of alternating material layers, and the carbon-containing hard mask covers the oxide cap, wherein the carbon-containing hard mask has one or more slots that allow the plasma effluent to enter the oxide cap, etching one or more features partially through the oxide cap with the plasma effluent through the one or more slots of the hard mask to create a tapered profile for the one or more features, the tapered profile of the one or more features characterized by a critical dimension at a bottom of the one or more features, wherein the tapered profile of the one or more features