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CN-122010043-A - Semiconductor device structure, preparation method thereof and semiconductor device array

CN122010043ACN 122010043 ACN122010043 ACN 122010043ACN-122010043-A

Abstract

The invention provides a semiconductor device structure, a preparation method thereof and a semiconductor device array, which relate to the technical field of semiconductor packaging, the semiconductor device structure comprises a substrate, a double-layer device layer, a back surface rewiring layer and a bonding pad, the substrate is configured to be grounded, and the front side of the substrate is provided with conductive silicon pillars penetrating to the back side, and the front side of the substrate is also provided with movable grooves. The double-layer device layer comprises a first device layer, a second device layer and a micro-motion structure, wherein the first device layer is arranged on the front surface of the substrate, the second device layer is positioned on one side, far away from the substrate, of the first device layer, and the micro-motion structure is arranged in the double-sided device layer and is positioned above the movable groove. The back rewiring layer is arranged on the back surface of the substrate, and the bonding pad is arranged on the surface of one side, far away from the substrate, of the second device layer. Compared with the prior art, the embodiment of the invention not only can meet the requirement of high-density wiring, but also can reduce the hidden trouble of packaging reliability, avoid thermal stress damage caused by packaging and ensure the performance of devices.

Inventors

  • CAO YINGCHAO
  • YANG XUEEN
  • SUN YONGHUAN
  • YI JINYANG
  • HUANG XIAOLEI

Assignees

  • 成都新易盛通信技术股份有限公司

Dates

Publication Date
20260512
Application Date
20260409

Claims (20)

  1. 1. A semiconductor device structure, comprising: A substrate (110) having a front side provided with conductive silicon pillars (111) penetrating to a back side, the conductive silicon pillars (111) comprising at least one first conductive silicon pillar (111 a) and at least one second conductive silicon pillar (111 b), and the front side of the substrate (110) further provided with a movable recess (112), the substrate (110) being configured to be grounded; A dual-layer device layer (120) comprising a first device layer (120 a), a second device layer (120 b) and a micro-motion structure (130), the first device layer (120 a) being disposed on the front side of the substrate (110), the second device layer (120 b) being located on a side of the first device layer (120 a) remote from the substrate (110), the micro-motion structure (130) being disposed in the dual-layer device layer (120) and being located above the active recess (112), the active recess (112) being configured as an active space for the micro-motion structure (130); a backside rewiring layer (140) disposed on the backside of the substrate (110) and electrically connected to the first conductive silicon pillars (111 a) and the second conductive silicon pillars (111 b); a bonding pad (150) disposed on a surface of the second device layer (120 b) away from the substrate (110) and electrically connected to the second device layer (120 b); The electrical signal received by the bonding pad (150) is transmitted to the back redistribution layer (140) through the first conductive silicon pillar (111 a), and then transmitted back to the double-layer device layer (120) through the second conductive silicon pillar (111 b), so as to form a U-shaped conductive loop for driving the micro-motion structure (130).
  2. 2. The semiconductor device structure of claim 1, wherein the active recess (112) has a depth of 50-400 μm.
  3. 3. The semiconductor device structure of claim 1 or 2, wherein the dual-layer device layer (120) further comprises an insulating layer (121) and an interlayer conductive plug (122), the insulating layer (121) being disposed at an interface of the first device layer (120 a) and the second device layer (120 b), the interlayer conductive plug (122) penetrating the insulating layer (121) to electrically connect the first device layer (120 a) and the second device layer (120 b).
  4. 4. A semiconductor device structure according to claim 3, wherein the first conductive silicon pillars (111 a) and the second conductive silicon pillars (111 b) are each electrically connected to the first device layer (120 a), the first conductive silicon pillars (111 a) being configured to transfer signals from the first device layer (120 a) to the backside redistribution layer (140), the second conductive silicon pillars (111 b) being configured to transfer signals from the backside redistribution layer (140) to the first device layer (120 a).
  5. 5. A semiconductor device structure according to claim 3, wherein the first conductive silicon pillars (111 a) and the second conductive silicon pillars (111 b) are each insulated from the substrate (110).
  6. 6. The semiconductor device structure of claim 5, wherein a first filled insulation trench (114 a) is disposed between the first conductive silicon pillar (111 a) and the substrate (110), and a second filled insulation trench (114 b) is disposed between the second conductive silicon pillar (111 b) and the substrate (110).
  7. 7. A semiconductor device structure according to claim 3, wherein the electrical signal is transmitted from the bond pad (150) to the second device layer (120 b), then to the first device layer (120 a) via the inter-layer conductive plug (122), then to the backside rerouting layer (140) via the first conductive silicon pillar (111 a), then back to the first device layer (120 a) via the second conductive silicon pillar (111 b), then to the second device layer (120 b) via the inter-layer conductive plug (122), such that the bond pad (150), the second device layer (120 b), the inter-layer conductive plug (122), the first device layer (120 a), the first conductive silicon pillar (111 a), the backside rerouting layer (140) and the second conductive silicon pillar (111 b) constitute the U-shaped conductive loop.
  8. 8. A semiconductor device structure according to claim 3, characterized in that the micro-motion structure (130) comprises a mirror (131) and a comb drive comprising a movable comb (132) and a stationary comb (133), the movable comb (132) and the mirror (131) being arranged in the first device layer (120 a), the stationary comb (133) being arranged in the second device layer (120 b), wherein the movable comb (132) is connected to a ground electrode (124) for grounding, the stationary comb (133) being connected to a driving electrode (123) for applying a driving voltage.
  9. 9. The semiconductor device structure of claim 8, wherein one end of the interlayer conductive plug (122) is embedded in the first device layer (120 a), and the other end of the interlayer conductive plug (122) is exposed on a surface of the second device layer (120 b) away from the first device layer (120 a).
  10. 10. The semiconductor device structure of claim 8, wherein one end of the interlayer conductive plug (122) is embedded in the second device layer (120 b), and the other end of the interlayer conductive plug (122) is exposed on a surface of a side of the first device layer (120 a) away from the second device layer (120 b).
  11. 11. The semiconductor device structure of claim 8, wherein one end of the interlayer conductive plug (122) is exposed to a side surface of the second device layer (120 b) remote from the first device layer (120 a), and the other end of the interlayer conductive plug (122) is exposed to a side surface of the first device layer (120 a) remote from the second device layer (120 b) and electrically connected to the conductive silicon pillar (111).
  12. 12. The semiconductor device structure of claim 8, wherein the first conductive silicon pillars (111 a) are in electrical contact with and insulated from regions corresponding to the drive electrodes (123) on the bilayer device layer (120), and the second conductive silicon pillars (111 b) are in electrical contact with and insulated from regions corresponding to the bond pads (150) on the bilayer device layer (120).
  13. 13. The semiconductor device structure of claim 12, wherein the front side of the substrate (110) is further provided with a first electrical isolation trench (113 a) and a second electrical isolation trench (113 b), the first electrical isolation trench (113 a) being looped around the first conductive silicon pillar (111 a), the second electrical isolation trench (113 b) being looped around the second conductive silicon pillar (111 b).
  14. 14. A semiconductor device structure according to claim 3, characterized in that the micro-motion structure (130) comprises a mirror (131) and a comb drive comprising a movable comb (132) and a fixed comb (133), the mirror (131) and the movable comb (132) being arranged in the second device layer (120 b), the fixed comb (133) being arranged in the first device layer (120 a), the movable comb (132) being connected to a ground electrode (124) for grounding, the fixed comb (133) being connected to a driving electrode (123) for applying a driving voltage.
  15. 15. A semiconductor device structure according to claim 3, wherein a first isolation channel (125) is disposed on the first device layer (120 a), a second isolation channel (126) is disposed on the second device layer (120 b), the first isolation channel (125) and the second isolation channel (126) are all surrounded by the interlayer conductive plug (122), and the first isolation channel (125) and the second isolation channel (126) are correspondingly communicated or arranged in a staggered manner.
  16. 16. An array of semiconductor devices comprising a plurality of semiconductor device structures according to any one of claims 1 to 15 arranged in two orthogonal directions.
  17. 17. A method of fabricating a semiconductor device structure according to claim 1, the method comprising: Providing a substrate (110); forming a conductive silicon column (111) and a movable groove (112) on the front surface of the substrate (110); forming a first isolation channel (125) on a front side of a dual-layer device wafer having a dual-layer device layer (120), wherein the dual-layer device layer (120) includes a first device layer (120 a) and a second device layer (120 b), the first isolation channel (125) being formed on the front side of the first device layer (120 a); Bonding a double-layer device wafer with a double-layer device layer (120) on the front surface of the substrate (110), wherein a first device layer (120 a) is bonded on the front surface of the substrate (110) and is electrically connected with the conductive silicon column (111), and a second device layer (120 b) is positioned on one side of the first device layer (120 a) away from the substrate (110) and is electrically connected with the first device layer (120 a); thinning the back surface of the substrate (110) and exposing the conductive silicon pillars (111) so that the conductive silicon pillars (111) penetrate to the back surface of the substrate (110); Forming a backside rerouting layer (140) on a backside of the substrate (110), wherein the backside rerouting layer (140) is electrically connected to the conductive silicon pillars (111); forming a bond pad (150) on a side surface of the second device layer (120 b) remote from the substrate (110), wherein the bond pad (150) is electrically connected to the second device layer (120 b); A jog structure (130) is formed in the second device layer (120 b) and the first device layer (120 a), wherein the jog structure (130) corresponds to the active recess (112).
  18. 18. The method of manufacturing a semiconductor device structure of claim 17, the dual-layer device layer (120) further comprising an insulating layer (121) disposed between the first device layer (120 a) and the second device layer (120 b), wherein prior to the step of forming a bond pad (150) on a side surface of the second device layer (120 b) remote from the substrate (110), the method further comprises: Thinning a side of the bilayer device wafer away from the substrate (110) and exposing the second device layer (120 b); an interlayer conductive plug (122) is formed in the second device layer (120 b), wherein one end of the interlayer conductive plug (122) is embedded in the first device layer (120 a), and the other end of the interlayer conductive plug (122) is exposed on one side surface, far away from the first device layer (120 a), of the second device layer (120 b).
  19. 19. The method of manufacturing a semiconductor device structure of claim 17, the bilayer device layer (120) further comprising an insulating layer (121) disposed between the first device layer (120 a) and the second device layer (120 b), wherein bonding a bilayer device wafer having a bilayer device layer (120) to the front side of the substrate (110) is preceded by the step of: An interlayer conductive plug (122) is formed in the first device layer (120 a), wherein one end of the interlayer conductive plug (122) is embedded in the second device layer (120 b), the other end of the interlayer conductive plug (122) is exposed to one side surface of the first device layer (120 a) away from the second device layer (120 b), and the interlayer conductive plug (122) is configured to be bonded to the conductive silicon pillar (111).
  20. 20. The method of fabricating a semiconductor device structure of claim 17, wherein the step of forming conductive silicon pillars (111) and active recesses (112) in the front side of the substrate (110) comprises: forming a conductive silicon column (111) on the front surface of the substrate (110); Planarizing the front surface of the substrate (110); forming an electrical isolation groove on the front surface of the substrate (110), wherein the electrical isolation groove is annularly arranged on the conductive silicon column (111); a movable recess (112) is formed in the front surface of the substrate (110).

Description

Semiconductor device structure, preparation method thereof and semiconductor device array Technical Field The invention relates to the technical field of semiconductor packaging, in particular to a semiconductor device structure, a preparation method thereof and a semiconductor device array. Background Microelectromechanical Systems (MEMS) micromirror technology plays a central role in modern fiber optic communication networks. By precisely controlling the deflection of the micro-mirror, the attenuation, switching and modulation of the light beam can be realized, and the micro-mirror can be widely applied to key devices such as an optical switch, an optical attenuator, an optical adjustable filter and the like. In particular, two-dimensional micromirror arrays, which are a core component in constructing an optoelectronic switch (OCS) in a data center network, are of vital importance. The optical communications industry has long been striving to develop optical switch solutions that are low cost, high port count, and have low switching times. In order to increase the channel capacity of a cross-connect system, the number of mirrors in the MEMS mirror matrix must be increased and the fill factor increased, a high fill factor being important for improving the optical channel shape and reducing the optical loss of the system. Conventional planar wiring schemes have a certain space limitation, and in order to break through the density limitation of planar wiring, the conventional improvement scheme generally adopts a Through Silicon Via (TSV) technology, vertically introduces a driving electrode of a micromirror into the bottom of a chip, and then directly mounts the chip onto a ceramic substrate or PCB board through a Flip-chip (Flip-chip) process. While this approach solves the wiring density problem, it introduces serious package reliability hazards and is prone to thermal stress damage. Disclosure of Invention The invention aims to provide a semiconductor device structure, a preparation method thereof and a semiconductor device array, which not only can meet the requirement of high-density wiring, but also can reduce the hidden trouble of packaging reliability, avoid thermal stress damage caused by packaging and ensure the performance of devices. The invention is realized by the following technical scheme: in a first aspect, an embodiment of the present invention provides a semiconductor device structure, including: a substrate, the front side of which is provided with a conductive silicon column penetrating to the back side, the conductive silicon column comprises at least one first conductive silicon column and at least one second conductive silicon column, the front side of the substrate is also provided with a movable groove, and the substrate is configured to be grounded; The double-layer device layer comprises a first device layer, a second device layer and a micro-motion structure, wherein the first device layer is arranged on the front surface of the substrate, the second device layer is positioned on one side, far away from the substrate, of the first device layer, the micro-motion structure is arranged in the double-layer device layer and above the movable groove, and the movable groove is configured as a movable space of the micro-motion structure; The back rewiring layer is arranged on the back of the substrate and is electrically connected with the first conductive silicon column and the second conductive silicon column; the bonding pad is arranged on one side surface of the second device layer, which is far away from the substrate, and is electrically connected with the second device layer; the electric signals received by the bonding pads are transmitted to the back surface rewiring layer through the first conductive silicon columns and then transmitted back to the double-layer device layer through the second conductive silicon columns, so that a U-shaped conductive loop is formed and used for driving the micro-motion structure. In an alternative embodiment, the depth of the active groove is 50-400 μm. In an alternative embodiment, the dual-layer device layer further includes an insulating layer disposed at an interface of the first device layer and the second device layer, and an interlayer conductive plug penetrating the insulating layer to electrically connect the first device layer and the second device layer. In an alternative embodiment, the first conductive silicon pillars and the second conductive silicon pillars are each electrically connected to the first device layer, the first conductive silicon pillars being configured to transfer signals from the first device layer to the backside rerouting layer, the second conductive silicon pillars being configured to transfer signals from the backside rerouting layer to the first device layer. In an alternative embodiment, the first conductive silicon pillar and the second conductive silicon pillar are each insulated from the substrate. In an