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CN-122016918-A - Interface thermal resistance testing method and testing device

CN122016918ACN 122016918 ACN122016918 ACN 122016918ACN-122016918-A

Abstract

The disclosure provides a method and a device for testing interface thermal resistance, and belongs to the technical field of semiconductor device testing. The testing method comprises the steps of obtaining actual cumulative structural function curves of a plurality of comparison samples of the semiconductor device, constructing a thermal solution model of the semiconductor device, and establishing a thermal network model corresponding to the thermal solution model, wherein the thermal network model is used for representing an equivalent thermal solution of a heat flow path from a heat generating junction to an environmental medium of the semiconductor device, optimizing parameters of the thermal network model through the actual cumulative structural functions of the comparison samples, and obtaining thermal resistance values of all interfaces in the semiconductor device according to the optimized thermal network model. The present disclosure may determine thermal resistance at different interfaces within a semiconductor device.

Inventors

  • TANG YAO

Assignees

  • 京东方华灿光电(浙江)有限公司

Dates

Publication Date
20260512
Application Date
20251223

Claims (10)

  1. 1. The method for testing the interface thermal resistance is characterized by comprising the following steps: Obtaining actual cumulative structural function curves of a plurality of comparison samples of a semiconductor device, wherein the semiconductor device comprises a substrate, a plurality of functional film layers positioned on the front surface of the substrate and a heat dissipation substrate connected with the back surface of the substrate, the plurality of comparison samples are identical to the film layer structure of the semiconductor device, the thickness of the substrate of one comparison sample is identical to the thickness of the substrate of the semiconductor device, the thickness of the substrate of each comparison sample is different, the actual cumulative structural function curves are obtained by carrying out transient thermal test on the comparison samples and are used for representing the functional relation of cumulative thermal resistance in the equivalent physical structure of the comparison samples with respect to cumulative thermal capacity on the heat flow path from a heating junction to an environmental medium in the comparison samples; constructing a thermal solution model of the semiconductor device, and establishing a thermal network model corresponding to the thermal solution model, wherein the thermal network model is used for representing an equivalent thermal solution of a heat flow path of the semiconductor device from a heat generating junction to an environmental medium; optimizing parameters of the thermal network model through actual cumulative structural functions of the comparison samples; And obtaining the thermal resistance value of the interface in the semiconductor device according to the optimized thermal network model.
  2. 2. The test method of claim 1, wherein the thermal solution model comprises sub-models that are stacked in sequence in one-to-one correspondence with the heat-dissipating substrate, the substrate, and the respective functional film layers; The establishing a thermal network model corresponding to the thermal solution model comprises the following steps: Mapping each sub-model in the thermal solution model into a thermal node formed by parallel connection of thermal resistance and thermal capacitance, wherein the thermal resistance value and the thermal capacitance value of the thermal node are calculated based on the geometric parameters and the thermophysical parameters of the layer structure corresponding to the sub-model; Mapping a contact interface between two adjacent sub-models in the thermal solution model into a pure thermal resistance node; And sequentially connecting the thermal nodes and the pure thermal resistance nodes in series according to the stacking sequence of the corresponding submodels to obtain the thermal network model.
  3. 3. The method of testing according to claim 2, wherein said optimizing parameters of said thermal network model by actual cumulative structural functions of each of said comparative samples comprises: Based on the thermal resistance value and the thermal capacitance value of the thermal network model and the thickness of the substrate of each comparison sample, generating a theoretical cumulative structural function curve of each comparison sample, wherein the theoretical cumulative structural function curve is a cumulative structural function curve calculated by the comparison sample based on the parameters of the thermal network model; Calculating an error between the theoretical cumulative structural function curve and the actual cumulative structural function curve for each of the comparative samples; and adjusting the thermal resistance value in the thermal network model according to the error until the error between the theoretical cumulative structural function curve and the corresponding actual cumulative structural function curve is within a required range.
  4. 4. A method of testing according to claim 3, wherein said adjusting the thermal resistance in the thermal network model based on the error comprises: Under the constraint condition, adjusting the thermal resistance of the contact interface so that the errors of all the comparison samples are smaller than a first threshold value and not smaller than a second threshold value; When the error is smaller than the first threshold and not smaller than the second threshold, adjusting thermal parameters of the layer structure corresponding to the sub-film type under the constraint condition until the sum of the errors of all the comparison samples is smaller than the second threshold, wherein the second threshold is smaller than the first threshold; and the constraint conditions comprise that the heat capacity corresponding to the submodels except the submodel corresponding to the substrate is the same in all the comparison samples, and the thermal resistance of the contact interface of the same submodel is the same.
  5. 5. The test method according to any one of claims 1-4, wherein the actual cumulative structural function curve is obtained by: Calculating to obtain a temperature rise cooling curve of junction temperature of each comparison sample along with time change based on voltage data in the transient cooling curve of each comparison sample and temperature sensitive parameter coefficients of the semiconductor device; According to the heating power applied when the temperature rise cooling curve and the transient cooling curve are obtained, calculating to obtain a transient thermal impedance curve; And transforming the transient thermal impedance curve to obtain the actual cumulative structural function curve.
  6. 6. The testing device is characterized by comprising a first determining module, a model building module, an optimizing module and a second determining module; The first determining module is configured to obtain an actual cumulative structural function curve of a plurality of comparison samples of a semiconductor device, where the semiconductor device includes a substrate, a plurality of functional film layers located on a front surface of the substrate, and a heat dissipation substrate connected to a back surface of the substrate, the plurality of comparison samples have a same film structure as the semiconductor device, and one of the comparison samples has a thickness that is the same as a thickness of the semiconductor device, and the thickness of the substrate of each of the comparison samples is different, where the actual cumulative structural function curve is obtained by performing a transient thermal test on the comparison samples, and is used to characterize a functional relationship of cumulative thermal resistance with respect to cumulative thermal capacity in an equivalent physical structure of the comparison samples on a thermal flow path from a heat generating junction to the environmental medium in the comparison samples; the model construction module is used for constructing a thermal solution model of the semiconductor device and establishing a thermal network model corresponding to the thermal solution model, wherein the thermal network model is used for representing an equivalent physical structure of a heat flow path between a heating junction and an environmental medium of the semiconductor device; the optimizing module is used for optimizing parameters of the thermal network model through actual cumulative structural functions of the comparison samples; And the second determining module is used for obtaining the thermal resistance value of each interface in the device according to the optimized thermal network model.
  7. 7. The test apparatus of claim 6, wherein the thermal solution model comprises sub-models stacked in a one-to-one and sequential manner with the heat sink base plate, the substrate, and the functional film layers, and wherein the thermal network model building module is further configured to: Mapping each sub-model in the thermal solution model into a thermal node formed by parallel connection of thermal resistance and thermal capacitance, wherein the thermal resistance value and the thermal capacitance value of the thermal node are calculated based on the geometric parameters and the thermophysical parameters of the structure corresponding to the sub-model; mapping a contact interface between any two sub-models in the thermal solution model into a pure thermal resistance node, wherein the thermal resistance value of the pure thermal resistance node is calculated based on the material geometric parameters and the thermophysical parameters of the contact interface corresponding to the thermal solution model; And sequentially connecting the thermal nodes and the pure thermal resistance nodes in series according to the stacking sequence of the corresponding submodels to obtain the thermal network model.
  8. 8. The test device of claim 7, wherein the optimization module is configured to: based on the thermal resistance value and the heat capacity value of the thermal network model and the thickness of the substrate of each comparison sample, generating a theoretical cumulative structural function curve of each comparison sample, wherein the theoretical cumulative structural function curve is a functional relation of cumulative thermal resistance generated by the comparison sample based on parameter calculation of the thermal network model and cumulative heat capacity, calculating errors between the theoretical cumulative structural function curve and the actual cumulative structural function curve of each comparison sample, and adjusting the thermal resistance value and the heat capacity value in the thermal network model according to the errors until the errors between the theoretical cumulative structural function curve and the corresponding actual cumulative structural function curve are within a required range.
  9. 9. The test apparatus of claim 8, wherein the optimization module is configured to adjust the thermal resistance of the contact interface under constraint conditions such that errors of all of the comparison samples are less than a first threshold and not less than a second threshold; When the error is smaller than the first threshold and not smaller than the second threshold, adjusting thermal parameters of the layer structure corresponding to the sub-film type under the constraint condition until the sum of the errors of all the comparison samples is smaller than the second threshold, wherein the second threshold is smaller than the first threshold; and the constraint conditions comprise that the heat capacity corresponding to the submodels except the submodel corresponding to the substrate is the same in all the comparison samples, and the thermal resistance of the contact interface of the same submodel is the same.
  10. 10. A computer device comprising a processor and a memory configured to store instructions executable by the processor, the processor configured to perform the method of testing the thermal interface resistance of any one of claims 1 to 5.

Description

Interface thermal resistance testing method and testing device Technical Field The disclosure belongs to the technical field of semiconductor device testing, and in particular relates to a testing method and a testing device for interface thermal resistance. Background Semiconductor devices are widely used in modern electronic systems with their excellent electrical performance. However, under high power density conditions, heat generated by the device active region (junction) can not be efficiently dissipated, resulting in a sharp rise in junction temperature, and therefore, thermal problems have become a critical bottleneck limiting device performance and reliability. In the related art, the thermal resistance of a semiconductor device is detected by employing an electrical method. The testing process is that a test voltage is applied to the semiconductor device to generate heat in the semiconductor device and raise the junction temperature. Waiting for the semiconductor device to reach a thermal steady state, i.e. the junction temperature no longer changes. In a very short time, the test voltage is turned off and a very small and non-self-heating measurement current is immediately applied to the device. And detecting to obtain the forward voltage drop at the moment, and calculating junction temperature and thermal resistance according to the forward voltage drop. However, the above method can only obtain a total and macroscopic thermal resistance value, and it is not known how heat is accumulated and transferred inside the device, that is, the thermal resistance of each interface inside the device cannot be distinguished. Disclosure of Invention The embodiment of the disclosure provides a method and a device for testing interface thermal resistance, which can definitely measure the thermal resistance of each interface inside a device. The technical scheme is as follows: The embodiment of the disclosure provides a testing method of interface thermal resistance, which comprises the steps of obtaining actual cumulative structural function curves of a plurality of comparison samples of a semiconductor device, wherein the semiconductor device comprises a substrate, a plurality of functional film layers positioned on the front side of the substrate and a heat dissipation substrate connected with the back side of the substrate, the plurality of comparison samples are identical to the film layers of the semiconductor device in structure, one of the comparison samples is identical to the semiconductor device in thickness, the comparison samples are different in thickness, the actual cumulative structural function curves are obtained by conducting transient thermal tests on the comparison samples and are used for representing the functional relation of cumulative thermal resistance in the equivalent physical structure of the comparison samples with respect to cumulative thermal capacity in a heat flow path from a heating junction to an environment medium, constructing a thermal network model corresponding to the semiconductor device, the thermal network model is used for representing the equivalent structure of the semiconductor device from the heating junction to the environment medium, and the thermal network model is optimized according to the thermal value of each thermal interface of the comparison samples after the thermal network model is optimized. In another implementation mode of the disclosure, the thermal solution model comprises sub-models which are in one-to-one correspondence with the heat dissipation substrate, the substrate and the functional film layers and are sequentially stacked, the building of the thermal network model corresponding to the thermal solution model comprises mapping each sub-model in the thermal solution model into a thermal node formed by parallel connection of thermal resistance and thermal capacitance, thermal resistance values and thermal capacitance values of the thermal node are calculated based on geometric parameters and thermal physical parameters of a layer structure corresponding to the sub-model, contact interfaces between two adjacent sub-models in the thermal solution model are mapped into a pure thermal resistance node, and the thermal nodes and the pure thermal resistance nodes are sequentially connected in series according to the stacking sequence of the corresponding sub-models to obtain the thermal network model. In still another implementation manner of the disclosure, the fitting optimization of the parameters of the thermal network model through the actual cumulative structural function of each comparative sample includes generating a theoretical cumulative structural function curve of each comparative sample based on a thermal resistance value and a thermal capacitance value of the thermal network model and a thickness of a substrate of each comparative sample, the theoretical cumulative structural function curve being a cumulative structural function cur