CN-122017327-A - Wide-range high-speed data acquisition system

CN122017327ACN 122017327 ACN122017327 ACN 122017327ACN-122017327-A

Abstract

The invention discloses a wide-range high-speed data acquisition system which comprises a signal acquisition front end, a preamplifier, a filter network, an A/D conversion module, an FPGA, an ARM processor and a dual-port RAM, wherein the ARM processor is used for writing sampling rate parameters and channel selection parameters, the FPGA is used for completing channel selection and sampling time sequence control based on the parameters and generating an A/D sampling clock through a clock module, the FPGA performs serial-parallel conversion on serial conversion data output by A/D and then writes the serial conversion data into the dual-port RAM, and the FPGA adopts a ping-pong buffer mechanism of at least two buffer areas and sends an interrupt notice to the ARM processor when the ARM processor is full, and the ARM processor reads the buffer data for local storage or network transmission.

Inventors

FENG MEI
TANG ZHIHUI
CUI WEI
LI YIN
DUAN JIAYU
WANG YUQING
CHEN SHUANGQIANG
FANG DENGFU
LI ZHIGANG
WEI YINGJING

Assignees

中国辐射防护研究院

Dates

Publication Date: 20260512
Application Date: 20251228

Claims (10)

1. A wide-range high-speed data acquisition system, comprising: The device comprises a signal acquisition front end for outputting an analog pulse signal, a pre-amplifier connected with the signal acquisition front end, a filter network connected with the pre-amplifier, an A/D conversion module connected with the filter network, an FPGA, an ARM processor and a dual-port RAM; The ARM processor is used for writing sampling rate parameters and channel selection parameters into the FPGA during system initialization; The FPGA comprises a PWM control module, a channel and sampling rate selection module, a clock module, an A/D sampling control module, a serial-parallel conversion module, a data storage control module and an ARM interface control module; The channel and sampling rate selection module generates a clock configuration instruction based on the sampling rate parameter, and the clock module generates an A/D sampling clock based on an external input clock; The A/D sampling control module outputs a conversion time sequence control signal to the A/D conversion module based on the channel selection parameter and acquires serial conversion data; The data storage control module writes the parallel sampling data into a corresponding buffer area of the dual-port RAM, and outputs an interrupt notice to the ARM processor when the buffer area is fully written; and the ARM interface control module decodes the access address of the ARM processor to realize the reading and writing of the ARM processor to the dual-port RAM, so that the ARM processor reads the sampling data and performs local storage or transmits the sampling data to an upper computer through a network.
2. The wide range high speed data acquisition system according to claim 1, wherein the dual port RAM is logically divided into at least a first buffer area and a second buffer area, wherein the data storage control module employs a ping-pong buffer write mechanism, and issues a first interrupt to the ARM processor after the first buffer area is full to notify the data of the first buffer area to be read out and switches the writing to the second buffer area, and issues a second interrupt to the ARM processor after the second buffer area is full to notify the data of the second buffer area to be read out and switches back to the first buffer area to realize continuous sampling and continuous transmission.
3. The wide-range high-speed data acquisition system according to claim 1, wherein the PWM control module comprises a single chip microcomputer and an isolation driving module, the single chip microcomputer is used for outputting PWM control signals, the isolation driving module is used for carrying out photoelectric isolation and driving on the PWM control signals and then outputting the PWM control signals to an on-off control end of the A/D conversion module so as to realize on-off control on the A/D conversion module, and the single chip microcomputer is used for carrying out read-write on an off-chip EEPROM through an I/O port simulation IIC bus so as to expand an external memory.
4. The wide-range high-speed data acquisition system according to claim 1, wherein the PWM control module comprises a counter for counting based on a clock signal of a set period to form a reference value, a determination circuit for determining an update direction of the reference value based on a duty ratio threshold, a count step setting circuit for providing an up-count step and a down-count step to the counter, and an upper limit setting circuit and a lower limit setting circuit for generating an upper limit and a lower limit of the reference value to clip the reference value.
5. The wide-range high-speed data acquisition system according to claim 1, wherein the PWM control module satisfies the following duty cycle calculation and reference value update relationship: Wherein, the Is a PWM duty cycle; Is a conduction count value; is a period count value; is the first The reference value after the secondary update; is the first The reference value after the secondary update; is the upper limit of the reference value; is the lower limit of the reference value; To increase the counting step length; For decreasing the count step size; Is a duty cycle threshold.
6. The wide-range high-speed data acquisition system according to claim 1, wherein the channel and sampling rate selection module comprises a register A and a register B, the ARM processor writes a word into the register A and the register B according to a target sampling channel and a target sampling rate, the clock module generates an A/D sampling clock corresponding to the word based on an external input clock, and the clock module satisfies: Wherein, the Sampling clock frequency for A/D; inputting a clock frequency for the outside; Frequency multiplication coefficients are PLL; is the division coefficient.
7. The system of claim 1, wherein the data storage control module is configured to write the sampled data of each sampling channel into the dual-port RAM in channel order and to write the sampled data into the dual-port RAM byte by byte in order from low byte to high byte, wherein the bit width of the sampled data of each channel is 24 bit, and the data storage control module outputs byte data for writing and a write control signal to drive the dual-port RAM to complete writing.
8. A wide-range high-speed data acquisition method, characterized in that the method is executed based on the wide-range high-speed data acquisition system according to any one of claims 1 to 7, and comprises the following steps: After the system is initialized, the ARM processor writes sampling rate parameters and channel selection parameters into the FPGA, the channel and sampling rate selection module of the FPGA generates a clock configuration instruction based on the sampling rate parameters, and the clock module generates an A/D sampling clock based on an external input clock; the A/D sampling control module outputs a conversion time sequence control signal based on the channel selection parameter so as to drive the A/D conversion module to complete sampling and output serial conversion data; The serial-parallel conversion module converts the serial conversion data into parallel sampling data; The data storage control module writes the parallel sampling data into the corresponding buffer area of the dual-port RAM, and outputs an interrupt notification to the ARM processor when the preset buffer area is fully written; And the ARM processor reads the dual-port RAM through an ARM interface control module after receiving the interrupt so as to finish the local storage of the sampled data or the network transmission to an upper computer for processing.
9. The method of claim 8, further comprising adaptively updating the reference value by the PWM control module based on a duty cycle threshold during sampling, and calculating the duty cycle and updating the reference value according to the following relationship: Wherein, the Is a PWM duty cycle; Is a conduction count value; is a period count value; is the first The reference value after the secondary update; is the first The reference value after the secondary update; is the upper limit of the reference value; is the lower limit of the reference value; To increase the counting step length; For decreasing the count step size; Is a duty cycle threshold.
10. A computer readable storage medium having stored thereon a computer program which, when executed by an ARM processor, causes the ARM processor to perform the wide range high speed data acquisition method of claim 8 or 9.

Description

Wide-range high-speed data acquisition system Technical Field The invention relates to the field of data acquisition, in particular to a wide-range high-speed data acquisition system. Background The wide-range high-speed data acquisition technology is widely applied to the scenes such as radiation detection, nuclear instrument measurement, industrial nondestructive detection, high-speed pulse signal analysis and the like. Taking radiation detection as an example, gamma rays enter a detector to generate photoelectric signals, forming analog pulses through a preamplifier, suppressing high-frequency noise and power frequency interference through a filter network, then carrying out high-speed sampling on the pulses by a high-resolution A/D converter, and providing sampled data to a rear-end processing unit to finish storage, transmission and further analysis and processing. Because the pulse signal has large amplitude span, random arrival and obvious transient characteristics, a data acquisition system generally has higher sampling rate and resolution, and also has wide dynamic range and stable clock quality, so as to meet the measurement index requirements of energy resolution, time resolution and the like. In the prior art, a common data acquisition architecture includes a combination scheme of "analog front end+high speed adc+processor (or DSP/FPGA)". The system is limited by the real-time performance, bus bandwidth and buffer structure of the processor, once the sampling rate is increased or the number of channels is increased, the problems that sampling data cannot be carried in time, sampling is lost due to buffer overflow, data transmission is discontinuous and the like easily occur, meanwhile, when the sampling channels and the sampling rates are required to be switched according to different application scenes, the system often needs to provide various working clocks in clock generation and distribution, and if clock jitter and delay control are poor, high-speed sampling precision and system stability are further affected. In addition, some applications also need on-off control and state management of sampling links or key devices, and if the coupling between the control and the acquisition links is unreasonable, the complexity of system implementation is increased and the reliability is reduced. Disclosure of Invention To achieve the above and other related objects, the present invention discloses a wide-range high-speed data acquisition system, comprising: The device comprises a signal acquisition front end for outputting an analog pulse signal, a pre-amplifier connected with the signal acquisition front end, a filter network connected with the pre-amplifier, an A/D conversion module connected with the filter network, an FPGA, an ARM processor and a dual-port RAM; The ARM processor is used for writing sampling rate parameters and channel selection parameters into the FPGA during system initialization; The FPGA comprises a PWM control module, a channel and sampling rate selection module, a clock module, an A/D sampling control module, a serial-parallel conversion module, a data storage control module and an ARM interface control module; The channel and sampling rate selection module generates a clock configuration instruction based on the sampling rate parameter, and the clock module generates an A/D sampling clock based on an external input clock; The A/D sampling control module outputs a conversion time sequence control signal to the A/D conversion module based on the channel selection parameter and acquires serial conversion data; The data storage control module writes the parallel sampling data into a corresponding buffer area of the dual-port RAM, and outputs an interrupt notice to the ARM processor when the buffer area is fully written; and the ARM interface control module decodes the access address of the ARM processor to realize the reading and writing of the ARM processor to the dual-port RAM, so that the ARM processor reads the sampling data and performs local storage or transmits the sampling data to an upper computer through a network. Preferably, the dual-port RAM is logically divided into at least a first buffer area and a second buffer area, the data storage control module adopts a ping-pong buffer write mechanism, and sends a first interrupt to the ARM processor after the first buffer area is fully written to inform the ARM processor of reading the data of the first buffer area and switch the writing of the second buffer area, and sends a second interrupt to the ARM processor after the second buffer area is fully written to inform the ARM processor of reading the data of the second buffer area and switch the data of the second buffer area back to the first buffer area, so that continuous sampling and continuous transmission are realized. Preferably, the PWM control module comprises a singlechip and an isolation driving module, wherein the singlechip is used for outputting PWM control s