CN-122017335-A - Power metering device and method based on synchronization of FPGA and GPS

CN122017335ACN 122017335 ACN122017335 ACN 122017335ACN-122017335-A

Abstract

The application discloses a power metering device and method based on synchronization of an FPGA and a GPS, and relates to the field of power metering. The device comprises a main processor, a coprocessor, an analog-to-digital converter and a GPS module, wherein the analog-to-digital converter synchronously and parallelly collects electric energy parameters of a power grid, a data collection and buffer memory module in the coprocessor converts the electric energy parameters into parallel data, the GPS module provides absolute time for an asynchronous clock source synchronization module to output second pulse signals, the asynchronous clock source synchronization module in the coprocessor dynamically calibrates clock bias by adopting a counter based on the absolute time to generate a time stamp for each frame of data collected by the analog-to-digital converter, an FFT processing module in the coprocessor carries out serial processing on the parallel data with the time stamp in a time division multiplexing mode by adopting hardware arbitration logic, and an electric energy quality analysis module in the main processor calculates power of the power grid according to FFT processing results. The application can realize power metering with high precision and low cost.

Inventors

Cao Yingshuang
FU MENG
WANG ZIWEI
LIU JING
WANG NA
Luo dai
ZHANG PENGFEI
GAO CONGZHE
CHEN TIANTIAN
DONG ZHEN
FAN YING
HUANG XIAOSHAN
Tian yifan

Assignees

国网上海市电力公司
北京理工大学

Dates

Publication Date: 20260512
Application Date: 20260227

Claims (10)

1. The power metering device based on the synchronization of the FPGA and the GPS is characterized by comprising a main processor, a coprocessor, an analog-to-digital converter and a GPS module, wherein the coprocessor is the FPGA; The analog-to-digital converter is used for synchronously and parallelly collecting electric energy parameters of the power grid, wherein the electric energy parameters comprise voltage data and current data; The coprocessor comprises a data acquisition and buffer module, an asynchronous clock source synchronous module and an FFT processing module, wherein the data acquisition and buffer module is used for converting the electric energy parameters into parallel data and buffering, the GPS module is used for providing absolute time for the asynchronous clock source synchronous module to output second pulse signals, the asynchronous clock source synchronous module is used for dynamically calibrating clock deviation by adopting a counter based on the absolute time and generating a time stamp for each frame of data acquired by the analog-to-digital converter, and the FFT processing module comprises an FFT IP core, wherein the FFT IP core is used for carrying out serial processing on the parallel data with the time stamp by adopting hardware arbitration logic in a time division multiplexing mode to obtain an FFT processing result; The main processor comprises an electric energy quality analysis module, wherein the electric energy quality analysis module is used for calculating the power of the power grid according to the FFT processing result and transmitting the power back to the data acquisition and buffer module.
2. The power metering device based on synchronization of FPGA and GPS according to claim 1, wherein the asynchronous clock source synchronization module specifically comprises: The system comprises a first counting unit, a second counting unit, a latch unit and a control unit, wherein the first counting unit is used for latching a first counting value and a second counting value, the first counting value is the instantaneous value of a counter when the rising edge of a second pulse signal of a GPS module arrives, and the second counting value is the instantaneous value of the counter when the rising edge of a synchronous output signal of the analog-digital converter arrives; a phase offset calculation unit for calculating a phase offset of the heterologous clock according to the first count value and the second count value; An absolute start time calculation unit, configured to calculate an absolute start time of a current sampling frame of the analog-to-digital converter according to the absolute time and the phase deviation; and the time stamp generating unit is used for calculating the final absolute time stamp of any sampling point in the current sampling frame of the analog-to-digital converter by accumulating the nominal sampling period of the analog-to-digital converter based on the absolute starting time.
3. The FPGA and GPS synchronization-based power metering device of claim 2, wherein the phase offset is calculated by the formula: φ=T_SYNC_latest-T_PPS_latest; wherein phi represents the phase offset, T_PPS_last represents the first count value, T_SYNC_last represents the second count value; the absolute start time is calculated by the following formula: T_Frame_Start=GPS_Time+φ/f_HighSpeed_Counter; Wherein, T_frame_Start represents absolute Start Time, GPS_Time represents absolute Time, f_ HIGHSPEED _counter represents clock frequency of a Counter; the calculation formula of the timestamp is as follows: Timestamp_N=T_Frame_Start+N×T_Sample; where timestamp_N represents the final absolute Timestamp of the nth Sample point in the current Sample frame of the analog-to-digital converter, and T_sample represents the nominal Sample period of the analog-to-digital converter.
4. The power metering device based on synchronization of FPGA and GPS according to claim 1, wherein the power quality analysis module is further configured to calculate a harmonic component and a negative sequence component of a power grid according to the FFT processing result, and transmit the harmonic component and the negative sequence component back to the data acquisition and buffering module.
5. The FPGA and GPS synchronized based power metering device of claim 4, wherein the main processor further comprises a carbon emission analysis module; the carbon emission analysis module is used for calculating carbon emission according to the power, the harmonic component, the negative sequence component and the carbon emission factor, and transmitting the carbon emission back to the data acquisition and cache module.
6. The power metering device based on synchronization of the FPGA and the GPS according to claim 5, further comprising a storage module; the storage module is to store the parallel data, the power, the harmonic component, the negative sequence component, the carbon emissions, and the time stamp.
7. The power metering device based on synchronization of FPGA and GPS according to claim 6, wherein the storage module comprises SRAM and FLASH; The SRAM is used for storing the parallel data, and the FLASH is used for storing the power, the harmonic component, the negative sequence component, the carbon emission amount and the time stamp.
8. The FPGA and GPS synchronized based power metering device of claim 1, wherein the co-processor further comprises an FMC slave interface module; and the FFT IP core sends the FFT processing result to the main processor through the FMC slave interface module.
9. The FPGA and GPS synchronized based power metering device of claim 5, wherein the main processor further comprises a communication module; The communication module is used for uploading the power, the harmonic component, the negative sequence component and the carbon emission to an upper computer.
10. The power metering method based on synchronization of the FPGA and the GPS is characterized in that the power metering method based on synchronization of the FPGA and the GPS is realized by adopting the power metering device based on synchronization of the FPGA and the GPS according to any one of claims 1 to 9, and the power metering method based on synchronization of the FPGA and the GPS comprises the following steps: Acquiring electric energy parameters of a power grid synchronously and parallelly acquired by an analog-to-digital converter, wherein the electric energy parameters comprise voltage data and current data; converting the electric energy parameters into parallel data and caching; Based on the absolute time of the output second pulse signal provided by the GPS module, dynamically calibrating clock deviation by adopting a counter, and generating a time stamp for each frame of data acquired by the analog-to-digital converter; And carrying out serial processing on the parallel data with the time stamp by adopting hardware arbitration logic in a time division multiplexing mode to obtain an FFT processing result, wherein the FFT processing result is used for calculating the power of the power grid.

Description

Power metering device and method based on synchronization of FPGA and GPS Technical Field The application relates to the field of power metering, in particular to a power metering device and method based on synchronization of an FPGA and a GPS. Background With the popularity of nonlinear loads, high-precision, broadband measurement of power quality (e.g., power) has become critical. In addition, in the smart grid, a high-precision time synchronization is required for distributed measurement units (such as PMU (synchrophasor measurement unit Phasor Measurement Unit)) to achieve wide-area state monitoring and fault analysis of the grid. Related high precision measurement schemes often face the challenge of synchronization. It is a technical difficulty how to precisely synchronize these two independent clock sources with frequency offset and time stamp each sampling point with absolute time stamp of nanosecond accuracy, while high-speed ADC (Analog-to-Digital Converter) typically uses independent crystal as sampling clock, and PPS (pulse per second, pulses Per Second) signal of external GPS (global positioning system ) is typically used as absolute time reference of the system. And secondly, a calculation bottleneck. The multi-channel data processing (such as FFT (fast fourier transform, fast Fourier Transform)) at high sampling rate requires huge computing resources, and the conventional MCU (micro controller, microcontroller Unit) is difficult to complete in real time, and the FPGA (field programmable gate array ) scheme using multi-channel FFT parallel processing consumes a lot of hardware logic resources, which is high in cost. In summary, how to implement power metering with high precision and low cost is a problem to be solved at present. Disclosure of Invention The application aims to provide a power metering device and a power metering method based on synchronization of an FPGA and a GPS, which can realize power metering with high precision and low cost. In order to achieve the above object, the present application provides the following. In a first aspect, the application provides a power metering device based on synchronization of an FPGA and a GPS, which comprises a main processor, a coprocessor, an analog-to-digital converter and a GPS module, wherein the coprocessor is the FPGA. The analog-to-digital converter is used for synchronously and parallelly collecting electric energy parameters of the power grid, wherein the electric energy parameters comprise voltage data and current data. The coprocessor comprises a data acquisition and buffer module, an asynchronous clock source synchronous module and an FFT processing module, wherein the data acquisition and buffer module is used for converting the electric energy parameters into parallel data and buffering, the GPS module is used for providing absolute time for outputting second pulse signals for the asynchronous clock source synchronous module, the asynchronous clock source synchronous module is used for dynamically calibrating clock deviation by adopting a counter based on the absolute time and generating a time stamp for each frame of data acquired by the analog-to-digital converter, and the FFT processing module comprises an FFT IP core and a hardware arbitration logic for the parallel data with the time stamps and performing serial processing in a time division multiplexing mode to obtain FFT processing results. The main processor comprises an electric energy quality analysis module, wherein the electric energy quality analysis module is used for calculating the power of the power grid according to the FFT processing result and transmitting the power back to the data acquisition and buffer module. In an embodiment, the asynchronous clock source synchronization module specifically includes the following units. The system comprises a first counting value and a second counting value, wherein the first counting value is the instantaneous value of the counter when the rising edge of the second pulse signal of the GPS module arrives, and the second counting value is the instantaneous value of the counter when the rising edge of the synchronous output signal of the analog-digital converter arrives. And the phase offset calculation unit is used for calculating the phase offset of the heterologous clock according to the first count value and the second count value. And the absolute start time calculation unit is used for calculating the absolute start time of the current sampling frame of the analog-to-digital converter according to the absolute time and the phase deviation. And the time stamp generating unit is used for calculating the final absolute time stamp of any sampling point in the current sampling frame of the analog-to-digital converter by accumulating the nominal sampling period of the analog-to-digital converter based on the absolute starting time. In one embodiment, the phase offset is calculated as follows. φ=T_SYNC_latest-T_PPS_latest; W