CN-122017345-A - Single pin impedance measurement system and phase offset compensation for single pin impedance measurement system

Abstract

Embodiments of the present disclosure relate to a single pin impedance measurement system and phase offset compensation for a single pin impedance measurement system. An impedance measurement system includes a signal generator including a memory and arranged to generate a digital test signal and at least one digital demodulation signal based on the memory, wherein the digital test signal has a first frequency and the at least one digital demodulation signal has a first frequency, a single pin for providing an analog test signal based on the digital test signal to a Device Under Test (DUT) and measuring an analog input signal in response to providing the analog test signal to the DUT, and a demodulator configured to obtain the at least one digital demodulation signal indicative of impedance and the at least one digital demodulation signal based on the first filtered digital signal of the input signal.

Inventors

• N. Gretzkus
• Shuman.T.

Assignees

• 瑞萨电子美国有限公司

Dates

Publication Date

20260512

Application Date

20251106

Priority Date

20241111

Claims (20)

1. 1. An impedance measurement system, comprising: a signal generator comprising a memory and arranged to generate a digital test signal and at least one digital demodulation signal based on the memory, wherein the digital test signal has a first frequency and the at least one digital demodulation signal has the first frequency; A single pin for providing an analog test signal based on the digital test signal to a device under test DUT and measuring an analog input signal in response to providing the analog test signal to the DUT, and A demodulator configured to obtain the following signals to produce at least one digital demodulated signal indicative of the impedance: a first filtered digital signal based on the input signal, and The at least one digitally demodulated signal.
2. 2. The impedance measurement system of claim 1, wherein the at least one demodulation signal comprises a first sinusoidal signal and a second sinusoidal signal, wherein the second sinusoidal signal is generated by phase shifting the first sinusoidal signal by 90 degrees.
3. 3. The impedance measurement system of claim 1, further comprising an input processing stage coupled to the single pin and the demodulator and configured to obtain the analog input signal and generate the first filtered digital signal based on the analog input signal.
4. 4. The impedance measurement system of claim 3, wherein the input processing stage comprises an oversampling ADC configured to generate a digital input signal based on the analog input signal.
5. 5. The impedance measurement system of claim 4, wherein the oversampling ADC is a 1-bit Σ - Δ ADC operating at a system frequency fs.
6. 6. The impedance measurement system of claim 4 wherein the input processing stage comprises a filter configured to filter the digital input signal to generate the first filtered digital signal.
7. 7. The impedance measurement system of claim 4, wherein the input processing stage comprises an amplifier configured to provide an amplified version of the analog input signal to the oversampling ADC.
8. 8. The impedance measurement system of claim 4, wherein the demodulator comprises an I/Q demodulator coupled to an output of the oversampling ADC, the I/Q demodulator configured to: Multiplying the first filtered digital signal with the first sinusoidal signal to generate a real component signal indicative of a real component of the analog input signal, and Multiplying the first filtered digital signal with the second sinusoidal signal to generate an imaginary component signal indicative of an imaginary component of the analog input signal, Wherein the at least one digital demodulation signal is based on the real component signal and/or the imaginary component signal.
9. 9. The impedance measurement system of claim 8, further comprising An integrator coupled to the output of the I/Q demodulator, wherein the integrator comprises a frequency response having a notch at a frequency of at least one harmonic of the at least one demodulated signal, Wherein the integrator is configured to filter the real component signal and the imaginary component signal to generate the at least one digital demodulation signal.
10. 10. The impedance measurement system of claim 1, further comprising a digital-to-analog converter DAC coupled to the signal generator to obtain the digital test signal and generate the at least one analog test signal.
11. 11. The impedance measurement system of claim 10 wherein the DAC has a sampling rate less than the system frequency fs.
12. 12. The impedance measurement system of claim 11, wherein the at least one analog test signal has a frequency set by a fraction of a system frequency fs times a prime number.
13. 13. The impedance measurement system of claim 12, wherein the DAC is coupled to one or more filters and/or one or more buffers configured to obtain an output from the DAC and generate the at least one analog test signal.
14. 14. The impedance measurement system of claim 1, wherein the memory comprises a LUT look-up table storing a set of predefined values at respective memory addresses for generating the digital test signal and the at least one digital demodulation signal.
15. 15. The impedance measurement system of claim 14, wherein the signal generator is configured to adjust the phase of the at least one digital demodulation signal and/or the digital test signal to correct a phase offset between the first filtered digital signal and the at least one digital demodulation signal.
16. 16. The impedance measurement system of claim 15, wherein the signal generator adjusts the phase of the at least one digital demodulation signal and/or the digital test signal by adding an address offset to a portion of a LUT that generates the at least one digital demodulation signal and/or the digital test signal.
17. 17. The impedance measurement system of claim 16, wherein the signal generator is configured to obtain the address offset from an external system to the impedance measurement system.
18. 18. The impedance measurement system of claim 16, further configured to determine the address offset during a calibration phase, wherein the calibration phase comprises coupling a DUT including only capacitive loading to the single pin.
19. 19. The impedance measurement system of claim 16, wherein the memory includes a set of predefined address offset values for respective temperature values.
20. 20. The impedance measurement system of claim 1, wherein the single pin is coupled to one or more sensors integrated in a steering wheel of a vehicle, wherein the impedance measurement system is configured to drive the one or more sensors to detect operator contact with the steering wheel.

Description

Single pin impedance measurement system and phase offset compensation for single pin impedance measurement system Cross Reference to Related Applications The present application claims the benefit of priority from british patent application 2416584.7 filed 11/2024. The entire disclosure of uk patent application 2416584.7 is incorporated herein by reference. Technical Field The present disclosure relates to single pin impedance measurement systems and phase offset compensation for single pin impedance measurement systems, and in particular, but not limited to, to single pin impedance measurement systems including a phase offset compensator configured to introduce an address offset to compensate for an unknown phase offset. The single pin impedance measurement system may be used with a steering device of a vehicle to implement a gesture-based human-machine interface system. Background To measure or calculate the impedance of the external device DUT (Device Under Test) under test, the system may generate measurements that represent the amplitude and phase (or real and imaginary components) of the impedance. To reduce the number of signal pins, each DUT should use only one connection to provide a "test signal" to the DUT and measure the result. A voltage may be applied to the DUT and the system may determine the impedance of the DUT by measuring the magnitude and phase of the current flowing through the DUT. Alternatively, a current may be applied to the DUT and the voltage across the DUT may then be measured to determine the amplitude and phase of the voltage signal. In order to be able to measure the real and imaginary components of the signal affected by the complex DUT, the test signal must be a time-varying signal, such as a signal pulse or sine wave. Typically, a sine wave is used because it has both amplitude and phase (real and imaginary components: "Re" and "Im"). Known systems typically implement I/Q demodulators to derive Re and Im. The amplitude and phase of the current is measured by the I/Q demodulator demodulating the signal measured across the DUT (either the current through the DUT or the voltage across the DUT). This measurement is performed by multiplying the measurement signal by a sine signal and a cosine signal of the same frequency. The output of the I/Q demodulator (after filtering) derives an in-phase quadrature signal at DC. The output is complex, including real and imaginary components. Amplitude is defined byThe phase is given by arctan%) Given. The sensitivity of the known system is limited, making it more susceptible to noise and parasitic effects, thus reducing the accuracy and reliability of the measurement results. Furthermore, because of internal signal delays that may be caused by propagation delays in frequency dependent signal processing or digital processing of analog amplifiers (similar to filter functions) used in systems that measure impedance, DUT-independent phase shifts may be introduced. For example, delays created by mixed signal devices such as analog-to-digital converters consistent with signal processing paths. Thus, the output from the I/Q demodulator may have a phase offset that is independent of the DUT. It is an object of the present disclosure to provide a single pin impedance measurement system for measuring the impedance of an external DUT with increased sensitivity, thereby reducing noise sensitivity and increasing measurement accuracy. Further, it is desirable to develop a system that can address phase shifts because correcting phase shifts increases accuracy. Disclosure of Invention According to a first aspect of the present disclosure there is provided an impedance measurement system comprising a signal generator comprising a memory, a single pin for providing an analogue test signal based on the digital test signal to a device under test DUT and measuring an analogue input signal in response to providing the analogue test signal to the DUT, and a demodulator arranged to generate at least one digital demodulation signal indicative of an impedance based on the first filtered digital signal of the input signal and the at least one digital demodulation signal, and to generate a digital test signal and at least one digital demodulation signal based on the memory, wherein the digital test signal has a first frequency and the at least one digital demodulation signal has a first frequency. According to a second aspect of the present disclosure, there is provided a single pin impedance measurement system comprising an oversampling analog to digital converter, a digital demodulator coupled to the analog to digital converter, and a memory configured to generate a test signal and one or more demodulation signals, wherein the test signal and the one or more demodulation signals are coherent such that the single pin impedance measurement system can simultaneously make phase measurements and amplitude measurements of the impedance signals. According to a third aspec