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CN-122017513-A - Semiconductor aging test method and system

CN122017513ACN 122017513 ACN122017513 ACN 122017513ACN-122017513-A

Abstract

The application relates to the technical field of semiconductor testing, and discloses a semiconductor element aging testing method and system. The method comprises the steps of completing loading and butt joint of an aging test board loaded with a component to be tested and a test station, starting an aging test flow and collecting test parameters of the component to be tested in real time, executing multi-level cross validation on the test parameters, outputting grading results comprising individual failure judgment and board level fault judgment, executing grading control according to the grading results, synchronously executing power supply cutting and physical isolation actions when the individual fails, triggering automatic replacement of a fault board when the board level fails, and executing finished product blanking and new board loading after the test is completed. The application improves the judging precision and the operation safety of the aging test, realizes the automatic continuous operation of the test flow, and effectively improves the test efficiency.

Inventors

  • DAI JIE
  • ZHANG HAIYU

Assignees

  • 杭州芯云海半导体有限公司

Dates

Publication Date
20260512
Application Date
20260303

Claims (10)

  1. 1. The aging test method for the semiconductor element is applied to an aging test system comprising an aging test board, a test station and an automatic feeding and discharging mechanism, and is characterized by comprising the following steps of: S1, finishing the butt joint of a feeding station and a testing station of an aging test board loaded with components to be tested, starting a preset aging test flow, and collecting test parameters of each component to be tested on the aging test board in real time; s2, performing multi-level cross validation on the collected test parameters, distinguishing and outputting grading judgment results, wherein the grading judgment results comprise individual failure judgment and board level fault judgment; s3, performing grading control according to the grading judgment result, if the individual failure judgment is output, synchronously performing power cutting-off action of a corresponding test channel and sinking physical isolation action of a test socket of a corresponding element to be tested; And S4, triggering the automatic feeding and discharging mechanism to execute a finished product discharging process after the burn-in test board completes a preset burn-in test process, and synchronously completing automatic feeding of the next burn-in test board.
  2. 2. The method according to claim 1, wherein the multi-level cross-validation comprises an individual anomaly pre-screening step for a single element to be tested, the individual anomaly pre-screening step comprising in particular: synchronously collecting the test parameters of a single element to be tested, wherein the test parameters comprise static electrical parameters, dynamic functional parameters and time sequence consistency parameters; And cross-comparing the currently acquired test parameters with the initial power-on reference parameters of the element to be tested and the pre-calibrated standard parameters of the elements in the same batch, and marking the element to be tested as a preliminary abnormal state when abnormal deviation occurs to the multiple types of parameters synchronously.
  3. 3. The method according to claim 2, wherein the multi-level cross-validation further comprises an anomaly type determination step for the element under test marked as preliminary anomaly, the anomaly type determination step comprising in particular: The test parameters of the to-be-tested element marked as the preliminary abnormal state are subjected to cross comparison with the normal parameters of clusters of adjacent to-be-tested elements with the same specification in the aging test board and the preset standard parameters of standard reference channels without to-be-tested elements in the board; If the test parameters of a plurality of the elements to be tested in the same area synchronously deviate, and the reference parameters of the standard reference channel synchronously deviate, the board-level environment of the aging test board is judged to be abnormal.
  4. 4. A method according to claim 3, wherein multi-node check-back cross-validation is performed on the component under test determined to be abnormal in the individual components under test, said multi-node check-back cross-validation specifically comprising the steps of: sequentially executing light load test mode retest, static parameter retest and retest after restarting the power failure on the element to be tested to obtain retest test parameters corresponding to each node; and cross-verifying the return detection test parameters of each node, and outputting the result of individual failure judgment when all the test results of the return detection nodes confirm abnormality.
  5. 5. A method according to claim 3, wherein board-level failure trend cross-validation is performed on a burn-in board where a component under test determined to be a board-level environmental abnormality of the burn-in board is located, said board-level failure trend cross-validation specifically comprising the steps of: Collecting data of an aging test board, wherein the data comprise distribution positions, abnormal parameter types and abnormal occurrence time sequences of abnormal elements to be tested in the aging test board, and simultaneously obtaining failure data of the aging test board in the same batch at other stations of the machine; and cross-comparing the acquired data of the aging test board with failure data of the aging test boards in the same batch at other stations of the same machine, and if the aging test board is abnormal in batches in a concentrated area, synchronous in parameters of the same type or the overall failure rate exceeds a preset threshold value, and the aging test boards in the same batch are not abnormal correspondingly, outputting a board level failure judgment result finally.
  6. 6. The method according to claim 1, wherein the step of synchronously performing the power-off action of the corresponding test channel and the sinking physical isolation action of the test socket of the corresponding element to be tested comprises the steps of: Controlling the power-off action and the sinking physical isolation action to be synchronously executed, wherein the execution time difference of the two actions is smaller than a preset time difference threshold; And performing secondary detection on the power-off state of the corresponding test channel and the sinking in-place state of the corresponding test socket, performing cross check on the secondary detection result and the individual failure judgment result, and performing system alarm and suspending the test flow of the aging test board if the verification is not passed.
  7. 7. The method according to claim 4, further comprising performing an abnormal state tracking of the component under test marked as transient disturbances in the multi-level cross-validation process, the abnormal state tracking comprising in particular the steps of: The sampling frequency and the cross verification frequency of the test parameters of the element to be tested marked as instantaneous interference are improved, and the change trend of the test parameters of the element to be tested is continuously collected and analyzed; And if the test parameters of the element to be tested are abnormal again, executing the multi-node check-back cross verification.
  8. 8. The method according to claim 1, further comprising performing a corresponding control action according to the real-time failure rate of the burn-in board, comprising the steps of: when the real-time failure rate of the aging test board reaches an early warning threshold value, triggering a system to pre-warn and calling the standby aging test board to the material level to be loaded in advance; when the real-time failure rate of the aging test board reaches a replacement threshold value or a board level fault judgment result is output, triggering the automatic feeding and discharging mechanism to execute a fault board replacement process.
  9. 9. The method according to claim 8, wherein the triggering the automatic loading and unloading mechanism to perform the fault board replacement process specifically comprises the following steps: firstly cutting off the total power supply of the fault aging test board, and then unlocking the docking mechanism of the fault aging test board and the test station; taking out the fault aging test board from the test station through an automatic feeding and discharging mechanism, and transferring the fault aging test board to a fault storage position to finish discharging and storing; The standby aging test board is transferred to a test station through an automatic feeding and discharging mechanism to finish butt joint and power-on self-test; And after the standby aging test board passes the self-inspection, starting the aging test flow of the test station.
  10. 10. A semiconductor device burn-in system, comprising: The test station is used for loading the burn-in test board and is electrically connected with the burn-in test board after loading, so as to provide a test environment and an electric signal path for the burn-in test of the element to be tested; The parameter acquisition unit is arranged at the test station, a signal acquisition end of the parameter acquisition unit is correspondingly and electrically connected with each element to be tested on the aging test board, a signal output end of the parameter acquisition unit is in communication connection with the main control unit, and is used for acquiring test parameters of each element to be tested on the aging test board in real time and transmitting the acquired test parameters to the main control unit; the channel protection execution unit is in communication connection with the main control unit, and the execution end of the channel protection execution unit corresponds to the test channels and the test sockets of the elements to be tested on the aging test board one by one and is used for synchronously executing the power-off action of the corresponding test channels and the sinking physical isolation action of the test sockets of the corresponding elements to be tested according to the control instruction issued by the main control unit; the automatic feeding and discharging mechanism is in communication connection with the main control unit and is used for executing the butt joint operation of the aging test board and the test station, the discharging operation of the aging test board and the replacement operation of the fault aging test board according to the control instruction issued by the main control unit; The main control unit is respectively connected with the parameter acquisition unit, the channel protection execution unit and the automatic feeding and discharging mechanism in a communication way and is used for receiving the test parameters transmitted by the parameter acquisition unit and outputting a grading control instruction to the channel protection execution unit and the automatic feeding and discharging mechanism.

Description

Semiconductor aging test method and system Technical Field The application relates to the technical field of semiconductor testing, in particular to a semiconductor aging testing method and system. Background In the manufacturing process of semiconductor elements, the aging test is a core process for screening the reliability of the elements and guaranteeing the mass production quality of products, and the existing semiconductor element aging test technology still has obvious defects in the application scene of batch test, wherein the prior art mostly adopts a single threshold comparison mode for failure judgment of the elements to be tested, is easy to be subjected to misjudgment caused by interference of test environments, cannot accurately distinguish individual failure of the elements and test board level faults, is difficult to adapt to the grading treatment requirements of batch test, and meanwhile, the prior art has single fault protection means, cannot realize reliable isolation of the failed elements, is easy to cause damage of the elements and test equipment due to fault diffusion, and the fault protection flow and feeding and discharging operations are mutually split, the board level faults are difficult to be subjected to manual shutdown intervention treatment, and the operation safety and the continuous test efficiency of the aging test are difficult to be considered, so that the mass production application requirements of the large-scale semiconductor element aging test cannot be met. Disclosure of Invention In order to solve or at least partially solve the above technical problems, the present application provides a semiconductor burn-in test method and system. In a first aspect, the present application provides a method for burn-in testing a semiconductor device, applied to a burn-in test system including a burn-in board, a test station, and an automatic loading and unloading mechanism, comprising the steps of: S1, finishing the butt joint of a feeding station and a testing station of an aging test board loaded with components to be tested, starting a preset aging test flow, and collecting test parameters of each component to be tested on the aging test board in real time; s2, performing multi-level cross validation on the collected test parameters, distinguishing and outputting grading judgment results, wherein the grading judgment results comprise individual failure judgment and board level fault judgment; s3, performing grading control according to the grading judgment result, if the individual failure judgment is output, synchronously performing power cutting-off action of a corresponding test channel and sinking physical isolation action of a test socket of a corresponding element to be tested; And S4, triggering the automatic feeding and discharging mechanism to execute a finished product discharging process after the burn-in test board completes a preset burn-in test process, and synchronously completing automatic feeding of the next burn-in test board. Optionally, the multi-level cross-validation includes an individual anomaly pre-screening step for a single element under test, the individual anomaly pre-screening step specifically including: synchronously collecting the test parameters of a single element to be tested, wherein the test parameters comprise static electrical parameters, dynamic functional parameters and time sequence consistency parameters; And cross-comparing the currently acquired test parameters with the initial power-on reference parameters of the element to be tested and the pre-calibrated standard parameters of the elements in the same batch, and marking the element to be tested as a preliminary abnormal state when abnormal deviation occurs to the multiple types of parameters synchronously. Optionally, the multi-level cross-validation further includes an anomaly type determining step for the element to be tested marked as the preliminary anomaly state, the anomaly type determining step specifically includes: The test parameters of the to-be-tested element marked as the preliminary abnormal state are subjected to cross comparison with the normal parameters of clusters of adjacent to-be-tested elements with the same specification in the aging test board and the preset standard parameters of standard reference channels without to-be-tested elements in the board; If the test parameters of a plurality of the elements to be tested in the same area synchronously deviate, and the reference parameters of the standard reference channel synchronously deviate, the board-level environment of the aging test board is judged to be abnormal. Optionally, for the to-be-tested element determined to be abnormal, performing multi-node check-back cross-validation, where the multi-node check-back cross-validation specifically includes the following steps: sequentially executing light load test mode retest, static parameter retest and retest after restarting the power failure on the ele