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CN-122017519-A - Processing method for obtaining static power consumption of chip

CN122017519ACN 122017519 ACN122017519 ACN 122017519ACN-122017519-A

Abstract

The application relates to the technical field of chip testing, in particular to a processing method for acquiring static power consumption of a chip. The method comprises the steps of S100, S200, S300, S400, S500 and S500, wherein a test result R of a target chip is obtained by using automatic test equipment ATE, the current coefficient a corresponding to the target chip is obtained, the equivalent temperature T c corresponding to the target temperature T 0 is obtained, the leakage current I 0 of the target chip when the working voltage of the target chip is V j,0 and the environment temperature is T c is obtained according to the a j , and the V j,0 ×I 0 is determined as the static power consumption of the target chip when the target chip is tested by using a system-level platform, wherein the target chip is enabled to work at the V j,0 and the temperature of the highest point of the target chip is T 0 . The application can acquire the static power consumption of the target chip under the platform test based on the test result of the target chip under the ATE test.

Inventors

  • LI WENWEN
  • LIU YANGBO
  • ZHAO QIN

Assignees

  • 沐曦集成电路(上海)股份有限公司

Dates

Publication Date
20260512
Application Date
20241031

Claims (7)

  1. 1. The processing method for obtaining the static power consumption of the chip is characterized by comprising the following steps of: S100, obtaining a test result R, R= (R 1 ,r 2 ,…,r j ,…,r n ),r j is a test result when the working voltage of the target chip obtained by using the ATE is the j-th preset voltage V j,0 , R j ＝(r j,1 ,r j,2 ),r j,1 is a test result when the environment temperature of the target chip obtained by using the ATE is the preset first temperature T 1,0 and the working voltage is V j,0 , R j,1 comprises a test result when the environment temperature of the target chip is T 1,0 and the working voltage is V j,0 , I j,1 ,r j,2 is a test result when the environment temperature of the target chip obtained by using the ATE is the preset second temperature T 2,0 and the working voltage is V j,0 , R j,2 comprises a leakage current I j,2 when the environment temperature of the target chip is T 2,0 and the working voltage is V j,0 , and j is the number of preset voltages; s200, obtaining a current coefficient a corresponding to the target chip, wherein a= (a 1 ,a 2 ,…,a j ,…,a n ),a j is a current coefficient corresponding to the j-th preset voltage corresponding to the target chip, and a j is according to the following Obtaining, wherein NT 1,0 is the average value of the temperatures of the target chip at each preset position when the ambient temperature is T 1,0 and the working voltage is V j,0 , and NT 2,0 is the average value of the temperatures of the target chip at each preset position when the ambient temperature is T 2,0 and the working voltage is V j,0 ; S300, acquiring an equivalent temperature T c ,T 0 corresponding to a target temperature T 0 as the temperature of the highest point of the temperature of the target chip when the target chip is tested by using a system level platform; S400, obtaining the leakage current I 0 of the target chip when the working voltage is V j,0 and the ambient temperature is T c according to a j , S500, determining V j,0 ×I 0 as static power consumption of the target chip when the target chip is tested by using the system-level platform and enabling the target chip to work at V j,0 and the temperature of the highest point of the temperature of the target chip is T 0 .
  2. 2. The method for processing the static power consumption of the chip as claimed in claim 1, wherein the acquiring process of T c comprises: S010, acquiring static power consumption BP of a sample chip at the highest point temperature of T 0 and the working voltage of V j,0 by using a system-level platform, wherein BP= (BP 1 ,BP 2 ,…,BP k ,…,BP q ),BP k is the static power consumption of a kth sample chip acquired by using the platform at the highest point temperature of T 0 and the working voltage of V j,0 , the value range of k is 1 to q, and q is the number of preset sample chips; s020, initializing a temperature variable e to be 0; S030, acquiring static power consumption DP e ,DP e ＝(DP e,1 ,DP e,2 ,…,DP e,k ,…,DP e,q ),DP e,k of a sample chip at the ambient temperature of T 0 -exDeltaT and at the working voltage of V j,0 by using ATE, wherein the static power consumption of a kth sample chip acquired by using ATE at the ambient temperature of T 0 -exDeltaT and at the working voltage of V j,0 ; s040, obtaining the e-th static difference sequence H e ,H e ＝(|BP 1 -DP e,1 |,|BP 2 -DP e,2 |,…,|BP k -DP e,k |,…,|BP q -DP e,q |); S050, if min (H e )>p 0 , updating e to be e+1, repeating S030-S040 until min (H e )≤p 0 , determining T 0 -exDeltaT as T c ; min () is the minimum value, and p 0 is the preset static power consumption threshold value).
  3. 3. The method of claim 1, wherein T 1,0 ℃ and T 2,0 are 75 ℃.
  4. 4. The method for processing the static power consumption of the chip according to claim 1, wherein T 0 = 100 ℃.
  5. 5. The method for obtaining static power consumption of a chip according to claim 4, wherein T 0 = 94 ℃.
  6. 6. The method according to claim 2, wherein BP k ＝V j,0 ×BI k ,BI k is a leakage current of the kth sample chip obtained using the platform at a peak temperature of T 0 and an operating voltage of V j,0 .
  7. 7. The method of claim 2, wherein DP e,k ＝V j,0 ×DI e,k ,DI e,k is a leakage current of a kth sample chip obtained using ATE at an ambient temperature of T 0 -eχΔt and an operating voltage of V j,0 .

Description

Processing method for obtaining static power consumption of chip Technical Field The invention relates to the technical field of chip testing, in particular to a processing method for acquiring static power consumption of a chip. Background The static power consumption of chips corresponding to respective voltages and temperatures in a product can be obtained using a platform (system level platform), but the workload of obtaining the static power consumption of each chip corresponding to respective voltages and temperatures in a product using a platform is too great. In the prior art, ATE (automatic test equipment) can measure the static power consumption of a chip at each voltage temperature in the period of CP (wafer) test and FT (final test), but no loading program runs on the chip during ATE test, and the temperatures of all points on the chip are relatively close. In the case of the platform test, the chip is run by the loader, and the temperature difference of different positions on the chip is large, so that the static power consumption obtained by using the ATE test and the platform test at the same temperature is different, and the static power consumption obtained by using the ATE test cannot be directly used as the static power consumption obtained by the platform test. How to obtain the static power consumption of a chip under a platform test based on the test result of the chip under an ATE test is a problem to be solved. Disclosure of Invention The invention aims to provide a processing method for acquiring static power consumption of a chip, so as to acquire the static power consumption of the chip under a platform test based on a test result of the chip under an ATE test. According to the invention, a processing method for acquiring static power consumption of a chip is provided, which comprises the following steps: S100, obtaining a test result R, R= (R 1,r2,…,rj,…,rn),rj is a test result when the working voltage of the target chip obtained by using the ATE is the j-th preset voltage V j,0, R j＝(rj,1,rj,2),rj,1 is a test result when the environment temperature of the target chip obtained by using the ATE is the preset first temperature T 1,0 and the working voltage is V j,0, R j,1 comprises a test result when the environment temperature of the target chip is T 1,0 and the working voltage is V j,0, I j,1,rj,2 is a test result when the environment temperature of the target chip obtained by using the ATE is the preset second temperature T 2,0 and the working voltage is V j,0, R j,2 comprises a leakage current I j,2 when the environment temperature of the target chip is T 2,0 and the working voltage is V j,0, and j is the number of preset voltages. S200, obtaining a current coefficient a corresponding to the target chip, wherein a= (a 1,a2,…,aj,…,an),aj is a current coefficient corresponding to the j-th preset voltage corresponding to the target chip, and a j is according to the followingThe obtained value is NT 1,0, which is the average value of the temperatures of the target chip at the preset positions when the ambient temperature is T 1,0 and the working voltage is V j,0, and NT 2,0, which is the average value of the temperatures of the target chip at the preset positions when the ambient temperature is T 2,0 and the working voltage is V j,0. S300, obtaining an equivalent temperature T c,T0 corresponding to the target temperature T 0 as the temperature of the highest point of the temperature of the target chip when the target chip is tested by using the system level platform. S400, obtaining the leakage current I 0 of the target chip when the working voltage is V j,0 and the ambient temperature is T c according to a j, S500, determining V j,0×I0 as static power consumption of the target chip when the target chip is tested by using the system-level platform and enabling the target chip to work at V j,0 and the temperature of the highest point of the temperature of the target chip is T 0. Compared with the prior art, the invention has at least the following beneficial effects: The invention can acquire the static power consumption of the target chip under the platform test based on the test result of the target chip under the ATE test, in particular, the invention acquires the leakage current of the target chip corresponding to each preset voltage and preset temperature under the ATE test, acquires the current coefficient a j of the target chip corresponding to each preset voltage based on the leakage current of the target chip corresponding to different preset temperatures under the same preset voltage, and can acquire the leakage current of the target chip under any temperature under the preset voltage corresponding to the target chip based on the current coefficient a j by substituting the equivalent temperature corresponding to the target temperature of the platform test into the test result The invention obtains the leakage current corresponding to the target temperature of the platform