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CN-122017520-A - Method and system for generating test sequence of electronic board card

CN122017520ACN 122017520 ACN122017520 ACN 122017520ACN-122017520-A

Abstract

The invention discloses a method and a system for generating an electronic board test sequence, and belongs to the technical field of Automatic Test (ATE) of electronic products. The method sequentially performs feature extraction on nodes through multi-mode engineering data access and map initialization, semantic inference and conflict arbitration based on weighted feature fusion, updates the connection relation of maps through weighted inference and conflict detection, dynamic limit value calculation based on physical routing parameters, test sequence ordering optimization based on Minimum Spanning Tree (MST) and platform adaptation code generation and verification, and generates a separated Switching file and an Action file. The method solves the problem that the long wiring is misjudged to be open circuit in high-precision test, reduces the misdetection rate to below 0.1%, simultaneously solves the problem of identifying the nonstandard naming pins, can identify more than 95% of test point attributes without manual intervention, and remarkably prolongs the service life of the expensive ATE switch matrix.

Inventors

  • DENG PENG
  • GAO HUI
  • Zhang Guanqin
  • DU BINGBING
  • Shang Rongzhu

Assignees

  • 安徽橡豫智能科技有限公司

Dates

Publication Date
20260512
Application Date
20251226

Claims (10)

  1. 1. The method for generating the test sequence of the electronic board card is characterized by being based on EDA map reconstruction and multi-mode semantic fusion, and comprises the following steps of: s1, accessing multi-mode engineering data and initializing a map, constructing a heterogeneous data access layer, analyzing a data source and establishing an initial equipment map to be tested, wherein nodes in the map represent pins, and edges in the map represent electrical connection; s2, carrying out semantic inference and conflict arbitration based on weighted feature fusion, extracting features of the nodes, and detecting and updating the connection relation of the atlas through weighted inference and conflict arbitration to obtain an updated atlas; s3, calculating a dynamic limit value based on physical routing parameters, calculating the dynamic limit value for a test group judged to be communicated based on the connection relation of the updated map, setting a static general limit value for an open circuit test group, binding the dynamic limit value and the static general limit value into the map, and obtaining a secondary updated map; s4, sequencing and optimizing a test sequence based on a minimum spanning tree or a specific network priority, and constructing a weighted complete graph based on the secondary updating map, wherein the weight is a switching state switching cost; S5, generating and verifying a platform adaptation code, loading a grammar template of a target platform based on the weighted complete graph, and generating a separated Switching file and an Action file.
  2. 2. The method of claim 1, wherein the data source of step S1 comprises document class data, logical class data, or physical class data.
  3. 3. The method of claim 2, wherein the parsing in step S1 includes extracting a pin definition table in PDF specifications and Excel using OCR and NLP, parsing a netlist file, extracting electrical connection logic relationships, parsing intelligent EDA data, extracting PCB lamination information, trace width, trace length and via number.
  4. 4. The method according to claim 1, wherein the feature extraction in step S2 includes extracting a three-dimensional feature vector for each node: Wherein For the text feature of the name, In order to physically abut the topological feature, To associate device features.
  5. 5. The method of claim 4, wherein the weighted inference of step S2 comprises inferring pin attributes using a weighted scoring mechanism.
  6. 6. The method of claim 5, wherein said conflict arbitration of step S2 includes automatically cutting the path in said map when the schematic is in conflict with the BOM based on a preset "manufacturability data first" rule.
  7. 7. The method of claim 1, wherein calculating the dynamic limit value in step S3 comprises calculating the dynamic limit value using physical modeling , In the following To test the fixture and interface path resistance, in To test the relay conduction internal resistance of the system switch matrix, wherein For wiring resistance, in Is a preset engineering safety tolerance.
  8. 8. The method of claim 7, wherein the trace resistance The calculation of (1) comprises: In which, in the process, In order to achieve a copper resistivity, the copper, Sequentially is the first Length, width and copper foil thickness of the segment traces.
  9. 9. The method of claim 1, wherein constructing the weighted completion graph in step S4 includes applying a minimum spanning tree or a traveler problem approximation algorithm to program a test execution order.
  10. 10. An electronic board test sequence generation system employing the method of any of claims 1-9, the system comprising: the EDA analysis engine is used for extracting physical routing parameters and topological relations; The semantic arbitration module is used for processing multi-source data conflict and deducing the electrical properties of the pins; the dynamic limit calculator is used for calculating the personalized resistance limit value of the network according to the physical parameters; the sequence optimizer is used for optimizing the execution sequence of the test steps based on a graph algorithm; Code generator, is used for outputting the engineering file adapting to the specific ATE software.

Description

Method and system for generating test sequence of electronic board card Technical Field The invention belongs to the technical field of Automatic Test (ATE) of electronic products, and particularly relates to a method and a system for generating a test sequence of an electronic board card. Background In the PCBA (printed circuit board assembly) manufacturing process, connectivity Test (connectivity Test) is a key element to verify physical manufacturing quality. With the development of high integration of automotive electronics (such as ADAS controllers) and communication devices, the number of test nodes (nodes) of a single board often exceeds 2000, and the network relationship is extremely complex. The prior art has the following remarkable defects: 1. "false failure" of static limits traditional methods typically set a uniform static limit (e.g., 10Ω) for all connectivity tests. However, in a practical high-density board, the physical resistance (TRACE RESISTANCE) caused by the long trace may be as high as several hundred milliohms, and the static limit value is very easily exceeded after the test fixture is overlapped, so that the good product is misjudged (FALSE FAIL). 2. Data source fragmentation and conflict engineering data is dispersed in schematic diagrams (PDF), BOM (Excel) and PCB Layout (Gerber/ODB++). The situation of "schematic show connection but BOM show no part (DNI/NC)" often occurs, and the manual check is very error-prone. 3. Lack of switch life optimization the test sequences generated by existing automatic generation tools are typically arranged randomly or alphabetically. In large matrix switching systems, frequent and unordered relay action can significantly shorten instrument life and increase test time. 4. Shallow nature of semantic understanding the prior art relies heavily on simple string matching (Regex). Nonstandard naming (e.g., naming "GND" as "RTN" or "VSS") cannot be handled, nor can electrical properties of unnamed Test points (Test pads) be inferred in conjunction with physical layout. Disclosure of Invention Aiming at the problems, the invention discloses a method and a system for generating an electronic board test sequence. The invention adopts the following technical scheme: an electronic board test sequence generation method based on EDA atlas reconstruction and multi-modal semantic fusion, comprising the steps of: S1, multi-mode engineering data access and map initialization are carried out, a heterogeneous data access layer is constructed, a data source is analyzed, an initial equipment map to be tested is established, nodes in the map represent pins, and edges in the map represent electrical connection; S2, carrying out feature extraction on the nodes based on semantic inference and conflict arbitration of weighted feature fusion, and detecting and updating the connection relation of the atlas through weighted inference and conflict arbitration to obtain an updated atlas; S3, calculating dynamic limit values based on dynamic limit values of physical routing parameters and connection relations of the updated patterns, calculating dynamic limit values for a test group judged to be connected, setting static general limit values for an open circuit test group, binding the dynamic limit values and the static general limit values into the patterns to obtain a secondary updated pattern, judging whether a theoretical value of network impedance is lower than a preset threshold value (for example, 1 omega), if so, triggering a four-wire system (Kelvin) test generation strategy, and respectively searching nodes closest to two ends of a device to be tested as sensing ends (Sense) and nodes farther away as forcing ends (Force) based on pattern topology; S4, based on the Minimum Spanning Tree (MST) or the test sequence ordering optimization of the specific network priority (such as the common ground GND network adopts a daisy chain DAISY CHAIN strategy), a weighted complete graph is constructed based on the secondary updating map, and the weight is the switching state switching cost; and S5, generating and verifying a platform adaptation code, loading a grammar template of the target platform, and generating a separated Switching file and an Action file. Design rule checking, particularly isolation testing steps between high voltage and sensitive networks, is performed. Further, the data sources in step S1 comprise document class data, logic class data or physical class data. Further, the parsing in step S1 includes extracting a pin definition table in PDF specification and Excel by utilizing OCR and NLP, parsing a netlist file, extracting an electrical connection logic relationship, parsing intelligent EDA data, and extracting PCB lamination information, wiring width, wiring length and via number. Further, the feature extraction in step S2 includes extracting a three-dimensional feature vector for each node: Wherein For the text feature of the name,In order to physically abu