CN-122017531-A - Integrated chip and method for autonomous testing and redundancy repair of inter-chip interconnection paths

Abstract

The invention provides an integrated chip for autonomous testing and redundancy repair of inter-chip interconnection paths, which comprises at least one chip, wherein each chip is provided with a group of interconnection ports for inter-chip interconnection and a port selection module, each interconnection port comprises a switching interface, an interconnection interface and a standby interconnection interface, the port selection module is used for connecting the interconnection interface with an internal logic circuit signal port according to selection signals, the at least one self-testing self-repair module is used for autonomously completing testing of the inter-chip interconnection paths under the action of switching signals and generating selection signals according to test results, and the self-testing self-repair module comprises a control circuit, a port selection signal generation module, a test vector comparison module, a core-chip switching module and a storage module.

Inventors

• PAN DONGFANG
• ZHANG SONGQI

Assignees

• 中国科学技术大学

Dates

Publication Date

20260512

Application Date

20260213

Claims (10)

1. 1. An integrated chip for inter-die interconnect routing autonomous testing and redundancy repair, comprising: At least one die, each die having a set of interconnect ports for inter-die interconnection and a port selection module, wherein the interconnect ports include a switch interface, an interconnect interface, and a standby interconnect interface; The self-test self-repairing module is used for automatically completing the test of the interconnection paths among the core particles under the action of the switching signals and generating the selection signals according to the test results; The self-test self-repair module comprises a control circuit, a port selection signal generation module, a test vector comparison module, a core particle exchange module and a storage module.
2. 2. The integrated chip of claim 1, wherein the integrated chip comprises, The control circuit comprises a finite state machine, and is used for performing state jump among seven states, namely an empty state, a test vector shifting state, a test ready state, a test finished state, a test result transmission state and a selection signal generation and storage state; The test vector generation module is used for storing test vectors and serially shifting the test vectors into a scan chain under the control of the control circuit; the test vector comparison module is used for storing expected test results and comparing actual test results with the expected test results; The core particle exchange module is used for receiving and transmitting state jump signals with other core particles through an exchange interface, so that test coordination among the core particles is realized; the port selection signal generation module is used for generating the selection signal according to a test result and a preset redundant interface replacement sequence; The storage module is used for storing the selection signal and providing the selection signal for the port selection module when the switch signal is closed.
3. 3. The integrated chip of claim 2, wherein the integrated chip comprises, The switching interface comprises an output interface and an input interface, and is used for synchronously transmitting state jump signals with the self-test self-repairing modules of other core grains; the interconnection interface is used for transmitting signals in a normal working state; and the standby interconnection interface is used for replacing the failed interconnection interface according to the selection signal when the interconnection interface fails.
4. 4. An integrated chip as claimed in claim 3, wherein the interconnect interfaces of the same type are placed between the spare interconnect interfaces such that after failure of a certain interconnect interface, the interconnect interface as a whole can be shifted up or down.
5. 5. The integrated chip of claim 2, wherein the integrated chip comprises, After the switch signal is started, the finite state machine jumps from an empty state to a test vector shift state; after the test vector displacement is finished, the control circuit controls the core particle exchange module to send a preparation completion signal to the corresponding connection core particle, and waits for receiving the preparation completion signal from the connection core particle, and both sides jump to a test state after receiving the preparation completion signal; After the test is completed, the control circuit sends a test completion signal to the connection core particle, waits for receiving the test completion signal from the connection core particle, and after both sides receive the test completion signal, shifts the test result to the test vector comparison module.
6. 6. The integrated chip of claim 5, wherein the integrated chip comprises, If a plurality of groups of test vectors exist, returning to a test vector shift state to repeat the test; if all the test vectors are tested, entering a test result transmission state.
7. 7. The integrated chip of claim 6, wherein the integrated chip comprises, In the test result transmission state, sending an output port channel test result of the connecting core particle to the connecting core particle through the core particle exchange module, receiving the output port channel test result of the connecting core particle, and entering into a generation selection signal and storage state after finishing the test; and in the state of generating and storing the selection signal, the port selection signal generating module generates the selection signal and stores the selection signal in the storage module, and after the completion, the port selection signal generating module externally sends out a completion signal and sets the finite state machine to be in an empty state.
8. 8. The integrated chip of claim 1, wherein the test vectors and expected test results are pre-stored in the test vector generation module and test vector comparison module during a design phase, and the redundant interface replacement order is a pre-set default order.
9. 9. A method for autonomous testing and redundancy repair of inter-die interconnect paths, applied to the integrated chip of any of claims 1-8, comprising: Responding to an external switch signal to enable the self-test self-repairing module, and controlling a finite state machine in a circuit to jump from an empty state to a test vector shift state; controlling a test vector generation module to serially shift a test vector into a core interconnection interface scanning chain to carry out test vector shifting, and sending a preparation completion signal to the connected core through an exchange interface; After receiving a preparation completion signal of the connected core particle, controlling the output port to output a scanning unit signal connected with the output port, and changing the value of the scanning unit signal connected with the input port according to the received signal to complete the test of the interconnection path; After the test is finished, a test finishing signal is sent to the connecting core particle through the exchange interface, and after the test finishing signal of the connecting core particle is received, the value of the scanning unit is shifted to the test vector comparison module in series to obtain an input port test result; if a plurality of groups of test vectors still exist in the test vector generation module, the test vector shifting step is returned to be repeatedly executed; If all the test vectors are tested, sending the output port channel test result of the connection core particle to the connection core particle through the exchange interface, and receiving the output port channel test result of the connection core particle; Generating and storing selection signals required by the port selection module according to the input port test result and the received output port channel test result and the preset redundant interface replacement sequence, and And sending out a completion signal, setting the finite state machine to be in an empty state, and completing the correct connection between the external interconnection interface and the signal port of the internal logic circuit by the port selection module according to the stored selection signal.
10. 10. The method of claim 9, wherein the step of determining the position of the substrate comprises, In the test vector shifting process, if the preparation completion signal of the connection core particle is not received, retransmitting the preparation completion signal after waiting for a preset clock cycle number; in the process of obtaining the test result, if the test completion signal of the connection core particle is not received, the test completion signal is resent after waiting for the preset clock cycle number.

Description

Integrated chip and method for autonomous testing and redundancy repair of inter-chip interconnection paths Technical Field The present disclosure relates to the field of integrated circuits and testing technologies, and in particular, to an integrated chip and a method for autonomous testing and redundancy repair of inter-die interconnection paths. Background As the evolution of semiconductor technology gradually approaches physical limits, the push rate of moore's law slows down significantly. For a long time, the conventional method of improving performance by continuously reducing the transistor size (process upgrading) or simply enlarging the area of a single chip is faced with the serious challenges of rapidly increasing development cost and decreasing marginal benefit of performance gain, and the cost-effectiveness ratio is increasingly reduced. To break through the bottleneck, heterogeneous integration technology of the core particle (Chiplet) has been developed and has become an important technical development direction in the latter molar age. This technique breaks down a complex system-on-chip (SoC) into multiple independently manufacturable chiplets (i.e., "die") with specific functionality. These cores can be manufactured separately using process nodes that are best suited for their function and cost, and then integrated into the same package through advanced packaging techniques (e.g., 2.5D/3D packaging) such as silicon interposer, rewiring layer, etc., thereby achieving higher system performance, more flexible design, and better overall cost. However, this advanced integration approach introduces new technical challenges, such as increased test complexity, package stacking and high density integration, while providing significant advantages, such that the inter-interconnect signal network between the die becomes extremely complex and difficult to access directly from the outside. The traditional chip testing method is difficult to carry out efficient and comprehensive electrical connectivity test and fault diagnosis on thousands of interconnection paths among the core particles after packaging. Yield loss risk high integration means a substantial increase in the number of die interconnect lines. Any one of the interconnect paths may fail in a circuit break, short or high resistance during fabrication and packaging, which may result in a functional failure of the entire integrated chip. Because of the huge number of interconnections, the risk of yield loss caused by interconnection defects is remarkably amplified, and the risk becomes a key bottleneck for limiting the mass production and yield improvement of multi-chip chips. However, the current method for detecting the connection between the core particles cannot meet the test requirements efficiently, accurately and at low cost. Disclosure of Invention In view of the above, to at least partially solve at least one of the above-mentioned technical problems, the present disclosure provides an integrated chip and method for inter-die interconnect path autonomous testing and redundancy repair. The technical proposal is as follows: According to an embodiment of one aspect of the disclosure, an integrated chip for autonomous testing and redundancy repair of inter-die interconnection paths is provided, and the integrated chip comprises at least one die, wherein each die is provided with a group of interconnection ports for inter-die interconnection and a port selection module, each interconnection port comprises a switching interface, an interconnection interface and a standby interconnection interface, the port selection module is used for connecting the interconnection interfaces with signal ports of internal logic circuits according to selection signals, the at least one self-test self-repair module is used for autonomously completing testing of the inter-die interconnection paths under the action of switching signals and generating selection signals according to test results, and the self-test self-repair module comprises a control circuit, a port selection signal generation module, a test vector comparison module, a die switching module and a storage module. According to the embodiment of the disclosure, a control circuit comprises a finite state machine, a test vector generation module, a test vector comparison module, a core particle exchange module and a port selection signal generation module, wherein the finite state machine is used for performing state jump among seven states of a null state, a test vector shift state, a test preparation state, a test completion state, a test result transmission state, a generation selection signal and a storage state, the test vector generation module is used for storing a test vector and serially moving the test vector into a scan chain under the control of the control circuit, the test vector comparison module is used for storing an expected test result and comparing an actual test result with the ex