CN-122017536-A - Digital integrated circuit fault diagnosis method and system

CN122017536ACN 122017536 ACN122017536 ACN 122017536ACN-122017536-A

Abstract

The invention relates to the technical field of digital integrated circuit pre-diagnosis and health management, and discloses a digital integrated circuit fault diagnosis method and system. The method comprises the steps of obtaining voltage fluctuation, current instantaneous change data and transmission delay time of an integrated circuit, obtaining a purified signal sequence through space-time integration and dynamic denoising, extracting time-frequency characteristics, completing phase correction, obtaining abnormal signal significant characteristic distribution, judging potential overload events and marking abnormal time when the threshold value is exceeded, tracing a fault propagation path, combining a module dependency relationship and a historical fault mode to lock a fault source preliminary interval, calculating comprehensive matching probability through multipath comparison, and screening an optimal tracing path to accurately position a circuit fault source position. The method can realize the high-efficiency and accurate diagnosis of the integrated circuit faults and meet the core requirements of operation and maintenance safety, timeliness and reliability.

Inventors

Peng Ruyong
LIN WENJIE
LIN QIUYING

Assignees

深圳中和城市科技有限公司

Dates

Publication Date: 20260512
Application Date: 20260401

Claims (9)

1. A method for diagnosing faults in a digital integrated circuit, comprising: Acquiring voltage fluctuation data, current instantaneous change data and delay time of data transmission of a digital integrated circuit; Performing time stamp alignment on the voltage fluctuation data and the current instantaneous change data, integrating space-time data by combining preset sensor space distribution information, denoising the integrated data, and forming a purifying signal sequence; Extracting time domain features and frequency domain features of the purified signal sequence, carrying out phase correction by combining the delay time length, and obtaining significant feature distribution of abnormal signals by carrying out clustering treatment and feature similarity calculation on the corrected features; If the significant feature distribution exceeds a preset fluctuation judgment threshold, judging that the potential circuit is overloaded, extracting signal pulse discrete points corresponding to the potential circuit overloaded, and obtaining a time mark of an abnormal event; According to the time mark, tracing back path nodes of fault propagation in the purifying signal sequence, constructing a space topological structure of the path nodes, determining a fault influence range boundary, and determining the propagation direction and a key influence area of an abnormal signal by combining with the sensor space distribution information; Analyzing the module dependency relationship and path node weight corresponding to the propagation direction and the key influence area, and determining a preliminary position interval of a fault source by combining a pre-acquired historical fault mode; calculating a path deviation value and positioning time precision of a real-time signal and a preset standard reference waveform according to a plurality of trace paths in the preliminary position interval, and calculating a comprehensive matching probability by combining the path deviation value and the positioning time precision; And screening the path with the highest comprehensive matching probability and the smallest path deviation value as an optimal backtracking path, and extracting the initial node coordinates of the optimal backtracking path to obtain the circuit fault root position.
2. The method for diagnosing a fault in a digital integrated circuit according to claim 1, wherein the steps of obtaining voltage fluctuation data, current transient variation data, and delay time of data transmission of the digital integrated circuit include: collecting operation state original data of the digital integrated circuit at high frequency through a sensor array, wherein the operation state original data comprises a voltage signal fluctuation range, current signal instantaneous change information and data transmission time sequence data; performing format standardization processing on the running state original data, and unifying data sampling granularity and numerical range; removing invalid records and random interference data in the running state original data to obtain preliminary processing data; and splitting and extracting voltage fluctuation data and current transient variation data from the preliminary processing data, and calculating the time difference of data transmission time sequence data to obtain the delay time of data transmission.
3. The method for diagnosing faults of a digital integrated circuit according to claim 1, wherein the performing time stamp alignment on the voltage fluctuation data and the current transient variation data, performing space-time data integration by combining preset sensor space distribution information, performing denoising processing on the integrated data, and forming a clean signal sequence includes: Extracting the timestamp marks of the voltage fluctuation data and the current instantaneous change data, and associating and binding the voltage data and the current data corresponding to the same timestamp; according to the preset sensor space distribution coordinates, mapping the correlated signal data to a physical space coordinate system to form space-time fusion data; Calculating the signal-to-noise ratio of the space-time fusion data and determining the interference degree of environmental noise; dynamically adjusting denoising parameters according to the noise interference level, and smoothing the space-time fusion data to remove environmental noise; The detail characteristics of the signals are reserved through a resolution compensation technology, and the processed signal fragments are spliced in time sequence to form a purified signal sequence.
4. The method for diagnosing faults of a digital integrated circuit according to claim 1, wherein the extracting time domain features and frequency domain features of the sequence of purified signals and performing phase correction in combination with the delay time length, and obtaining significant feature distribution of abnormal signals by performing clustering processing and feature similarity calculation on the corrected features includes: extracting time domain features and frequency domain features from the purified signal sequence; comparing the delay time length with a preset delay threshold, and if the delay time length exceeds the delay threshold, performing phase alignment correction on the frequency domain characteristics; Clustering the corrected time domain features and frequency domain features to divide feature clusters; calculating the feature similarity among the feature clusters, screening the clusters with the similarity higher than a preset similarity threshold, integrating the screened feature clusters, and constructing a feature mapping matrix to obtain the remarkable feature distribution of the abnormal signals.
5. The method for diagnosing a fault in a digital integrated circuit according to claim 1, wherein if the significant feature distribution exceeds a preset fluctuation determination threshold, determining that a potential circuit is overloaded, extracting discrete points of signal pulses corresponding to the potential circuit is overloaded, and obtaining a time stamp of an abnormal event includes: Calculating the energy density of the salient features distributed in a multidimensional feature space; comparing the energy density with a preset fluctuation judgment threshold, and judging that the potential circuit is overloaded if the energy density exceeds the fluctuation judgment threshold; Extracting signal pulses corresponding to the potential circuit overload event from the purified signal sequence, and determining discrete sampling points of the pulses; and calculating the time mark of the abnormal event according to the sampling time of the discrete sampling point.
6. The method for diagnosing faults in a digital integrated circuit according to claim 1, wherein the steps of tracing path nodes of fault propagation in the purified signal sequence according to the time stamp, constructing a spatial topology of the path nodes, determining a boundary of a fault influence range, and determining a propagation direction and a critical influence area of an abnormal signal by combining the sensor spatial distribution information include: intercepting local waveform data in the purifying signal sequence according to the time mark, identifying amplitude jump points in waveforms, and marking the amplitude jump points as fault propagation path nodes; Projecting the path nodes to a preset sensor space distribution coordinate system to form a space node set with a time stamp; constructing a space topological structure based on the coordinate distribution of the space node set, analyzing the space topological structure through a density clustering algorithm, and determining a fault influence range boundary; extracting a time stamp sequence of the space node set, and constructing a vector track pointing to the latest time stamp node from the earliest time stamp node; And combining the sensor space distribution information with the vector track to determine the propagation direction of the abnormal signal and the key influence area.
7. The method for diagnosing a fault in a digital integrated circuit according to claim 1, wherein the analyzing the module dependency relationship and path node weight corresponding to the propagation direction and the critical influence area, and determining the preliminary location interval of the fault source by combining the previously acquired historical fault mode, includes: according to the propagation direction and the key influence area, circuit topology structure data are called, and a module dependency relation matrix is constructed; Mapping the fault propagation path nodes to the module dependency relation matrix, and calculating weight values of the nodes; Extracting the distribution map features formed by the weight values, matching the distribution map features with a pre-acquired historical fault mode, and performing cluster analysis on the matched historical fault source coordinates to generate a high-density coordinate cluster; and (3) taking the high-density coordinate cluster as a core to define a preliminary position interval of a fault source.
8. The method for diagnosing a fault in a digital integrated circuit according to claim 1, wherein calculating a path deviation value and a positioning time precision of a real-time signal and a preset standard reference waveform according to a plurality of trace paths in the preliminary location interval, and calculating a comprehensive matching probability by combining the path deviation value and the positioning time precision comprises: generating a plurality of candidate backtracking paths based on the preliminary location interval and the circuit topology; calculating Euclidean distance between the real-time signal on each candidate trace-back path and a preset standard reference waveform to obtain a path deviation value; Analyzing the time difference between the abnormal triggering time of the signal and the issuing time of the control instruction to obtain positioning time precision; And distributing preset weight coefficients for the path deviation value and the positioning time precision, and weighting and calculating the comprehensive matching probability of each candidate backtracking path.
9. A digital integrated circuit fault diagnosis system, comprising: The data acquisition module is used for acquiring voltage fluctuation data, current instantaneous change data and delay time of data transmission of the digital integrated circuit; The preprocessing module is used for performing time stamp alignment on the voltage fluctuation data and the current instantaneous change data, integrating space-time data by combining preset sensor space distribution information, and denoising the integrated data to form a purified signal sequence; The feature extraction module is used for extracting time domain features and frequency domain features of the purified signal sequence, carrying out phase correction by combining the delay time length, and obtaining the remarkable feature distribution of the abnormal signal by carrying out clustering treatment and feature similarity calculation on the corrected features; the abnormality judgment module is used for judging a potential circuit overload event if the significant characteristic distribution exceeds a preset fluctuation judgment threshold value, extracting a signal pulse discrete point corresponding to the potential circuit overload event, and obtaining a time mark of the abnormal event; the path tracing module is used for tracing path nodes of fault propagation in the purifying signal sequence according to the time marks, constructing a space topological structure of the path nodes, determining a fault influence range boundary, and determining the propagation direction and a key influence area of an abnormal signal by combining the sensor space distribution information; The source positioning module is used for analyzing the module dependency relationship and path node weight corresponding to the propagation direction and the key influence area, and determining a preliminary position interval of the fault source by combining a pre-acquired historical fault mode; The probability calculation module is used for calculating the path deviation value and the positioning time precision of the real-time signal and the preset standard reference waveform according to the plurality of trace paths in the preliminary position interval, and calculating the comprehensive matching probability by combining the path deviation value and the positioning time precision; And the path screening module is used for screening the path with the highest comprehensive matching probability and the smallest path deviation value as the optimal backtracking path, extracting the initial node coordinates of the optimal backtracking path and obtaining the circuit fault root position.

Description

Digital integrated circuit fault diagnosis method and system Technical Field The invention relates to the technical field of digital integrated circuit pre-diagnosis and health management, in particular to a digital integrated circuit fault diagnosis method and system. Background At present, in the field of digital integrated circuit pre-diagnosis and health management, along with the continuous improvement of integrated circuit integration level and continuous expansion of complex application scenes, a digital integrated circuit is used as a core component of an electronic system, and the stable operation of the digital integrated circuit is directly related to equipment reliability and operation and maintenance cost control. Existing digital integrated circuit fault diagnosis methods in industry mainly rely on single signal detection or off-line analysis means, such as voltage fluctuation monitoring through a single-point sensor, or fault state judgment by simple waveform comparison, or signal time-space correlation and fault propagation rules are ignored. However, this approach presents significant drawbacks in complex operating environments. Because of limited single signal detection coverage, the global abnormal characteristics are difficult to capture, the offline analysis has hysteresis, is influenced by the interference of environmental noise, is easy to miss and judge micro faults or misjudge interference signals, and lacks the dynamic traceability of fault propagation paths, particularly in a complex integrated circuit with high density and multiple modules, the fault sources are difficult to quickly locate. In summary, the prior art is difficult to realize accurate and efficient diagnosis of faults of the digital integrated circuit, and the core requirements of the pre-diagnosis and health management field on the operation and maintenance safety, timeliness and reliability of the integrated circuit cannot be met. Disclosure of Invention The invention provides a digital integrated circuit fault diagnosis method and a system, which realize accurate and efficient diagnosis of digital integrated circuit faults and meet the core requirements of the pre-diagnosis and health management field on the operation and maintenance safety, timeliness and reliability of integrated circuits. In order to solve the above technical problems, the present invention provides a method for diagnosing faults of a digital integrated circuit, including: Acquiring voltage fluctuation data, current instantaneous change data and delay time of data transmission of a digital integrated circuit; Performing time stamp alignment on the voltage fluctuation data and the current instantaneous change data, integrating space-time data by combining preset sensor space distribution information, denoising the integrated data, and forming a purifying signal sequence; Extracting time domain features and frequency domain features of the purified signal sequence, carrying out phase correction by combining the delay time length, and obtaining significant feature distribution of abnormal signals by carrying out clustering treatment and feature similarity calculation on the corrected features; If the significant feature distribution exceeds a preset fluctuation judgment threshold, judging that the potential circuit is overloaded, extracting signal pulse discrete points corresponding to the potential circuit overloaded, and obtaining a time mark of an abnormal event; According to the time mark, tracing back path nodes of fault propagation in the purifying signal sequence, constructing a space topological structure of the path nodes, determining a fault influence range boundary, and determining the propagation direction and a key influence area of an abnormal signal by combining with the sensor space distribution information; Analyzing the module dependency relationship and path node weight corresponding to the propagation direction and the key influence area, and determining a preliminary position interval of a fault source by combining a pre-acquired historical fault mode; calculating a path deviation value and positioning time precision of a real-time signal and a preset standard reference waveform according to a plurality of trace paths in the preliminary position interval, and calculating a comprehensive matching probability by combining the path deviation value and the positioning time precision; And screening the path with the highest comprehensive matching probability and the smallest path deviation value as an optimal backtracking path, and extracting the initial node coordinates of the optimal backtracking path to obtain the circuit fault root position. In a second aspect, the present invention provides a digital integrated circuit fault diagnosis system, comprising: The data acquisition module is used for acquiring voltage fluctuation data, current instantaneous change data and delay time of data transmission of the digital integrated ci