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CN-122017667-A - Method for detecting and analyzing defects of interconnection hole chain of micro-bump bonding integrated chip

CN122017667ACN 122017667 ACN122017667 ACN 122017667ACN-122017667-A

Abstract

The application discloses a high-efficiency detection method for defects of a micro-bump bonding integrated chip interconnection hole chain, which mainly comprises the steps of carrying out direct current electric test on the interconnection hole chain, calculating an interconnection hole chain resistance value according to a direct current test result, judging an abnormal resistance value, picking out the interconnection hole chain with short circuit or open circuit according to the abnormal value, scribing the interconnection hole chain structure with short circuit or open circuit from the middle of a bump through a scribing process, attaching the bonding integrated chip with the scribing interconnection hole chain structure on a section polishing clamp, keeping the section flush with a polishing disc, carrying out section polishing on the scribed whole interconnection hole chain structure, cleaning the polished bonding integrated chip, checking the interconnection hole chain section by using an optical microscope, screening the abnormal point and analyzing the interconnection hole chain bonding defects by using detection.

Inventors

  • WANG FEI
  • QIAO GUANZHONG
  • DAI JIABIN
  • KONG YUECHAN

Assignees

  • 中国电子科技集团公司第五十五研究所

Dates

Publication Date
20260512
Application Date
20260112

Claims (10)

  1. 1. The method for detecting and analyzing the interconnection hole chain defects of the micro-bump bonding integrated chip is characterized in that the micro-bump bonding integrated chip comprises a plurality of groups of interconnection hole chain structures (14), each group of interconnection hole chain structures (14) is formed by bonding a first under bump metal (4) and a first metal bump (6) which are positioned on a first chip (15) to be bonded with a second under bump metal (8) and a second metal bump (7) which are positioned on a second chip (16) to be bonded, both ends of each group of interconnection hole chain structures (14) are respectively provided with an interconnection hole chain test electrode (13), and the method for detecting and analyzing the interconnection hole chain defects comprises the following steps: s1, performing direct-current electrical testing on each group of interconnection hole chain structures (14) by using a direct-current detection probe platform through the interconnection hole chain testing electrode (13), and judging and marking the interconnection hole chain structures (14) with short circuits or open circuits according to data of the direct-current electrical testing; S2, utilizing a scribing device capable of positioning a scribing position to scribe a marked interconnection hole chain structure (14) with short circuit or open circuit vertically downwards along the transverse central line of the interconnection hole chain structure (14) from the top of the micro-bump bonding integrated chip so as to form an interconnection hole chain structure section (11); S3, polishing the cross section (11) of the interconnection hole chain structure by using a cross section polishing device, specifically, placing the micro-bump bonding integrated chip with the interconnection hole chain structure (14) with short circuit or open circuit after dicing into the cross section polishing device, and enabling the cross section (11) of the interconnection hole chain structure exposed by dicing to be attached to a polishing disk for polishing until the cross section (11) of the interconnection hole chain structure is flat and smooth; s4, cleaning the polished micro-bump bonding integrated chip, specifically, sequentially placing the polished micro-bump bonding integrated chip into acetone and absolute ethyl alcohol for soaking, removing polishing particles and polishing liquid, flushing with deionized water after soaking, and drying or drying with nitrogen; S5, checking the cleaned cross sections (11) of the interconnection hole structures of the micro-bump bonding integrated chip by using an optical microscope, checking the cross sections of bonding bumps formed by the first metal bumps (6) and the second metal bumps (7) one by one, finding out the short circuit or disconnection points (12) of the bonding bumps, and marking; S6, amplifying the marked short circuit or disconnection point (12) of the bonding salient point by utilizing an electron microscope, scanning and shooting an amplified defect photo, and determining the specific position and the specific type of the generation of the interconnection hole chain structure defect according to the amplified defect photo.
  2. 2. A method for detecting and analyzing defects of a micro bump bonding integrated chip interconnection pore chain according to claim 1, wherein, The step S1 of judging and marking the interconnected pore chain structure (14) with short circuit or open circuit according to the data of the direct current electric test comprises the following steps: The data of the DC electrical test comprises test current and test voltage of the interconnection hole chain structure (14), a test resistance value of the interconnection hole chain structure (14) is calculated according to the test current and the test voltage, the test resistance value is compared with a normal resistance value of the interconnection hole chain structure (14), if the test resistance value is more than 1 order of magnitude higher than the normal resistance value, the interconnection hole chain structure (14) is judged to have an abnormal disconnection, and if the test resistance value is more than 1 order of magnitude lower than the normal resistance value, the interconnection hole chain structure (14) is judged to have an abnormal short circuit, and the interconnection hole chain structure (14) with the short circuit or the disconnection is marked.
  3. 3. A method for detecting and analyzing defects of a micro bump bonding integrated chip interconnection pore chain according to claim 1, wherein, In S2, the scribing device capable of positioning the scribing position is a grinding wheel scribing machine or a laser scribing machine.
  4. 4. A method for detecting and analyzing defects of a micro bump bonding integrated chip interconnection pore chain according to claim 1, wherein, In S3, the polishing is mechanical polishing or chemical polishing, and the polishing solution or abrasive used does not chemically react with the electroplated metal of the interconnected pore chain structure (14).
  5. 5. A method for detecting and analyzing defects of a micro bump bonding integrated chip interconnection hole chain according to claim 1 is characterized in that, And S4, soaking the micro-bump bonded integrated chip in acetone for 5-20min, and soaking in absolute ethyl alcohol for 3-20min.
  6. 6. The method for detecting and analyzing the defects of the interconnection links of the micro-bump bonded integrated chip according to claim 1, wherein in S6, the electron microscope is a scanning electron microscope, and the scanning electron microscope can amplify the short circuit or disconnection point (12) of the bonding bump on the bonding bump to 1000 times or more.
  7. 7. The method for detecting the defects of the interconnection pore chain of the micro-bump bonding integrated chip according to claim 1, wherein the method for manufacturing the interconnection pore chain structure of the micro-bump bonding integrated chip is as follows: s1', sputtering metal on the surface of a first substrate (1) to manufacture a first electroplating seed layer (2); S2', spin-coating photoresist on the first electroplating seed layer (2), and photoetching a first under bump metal of the interconnection hole chain structure (14) and an interconnection hole chain test electrode photoetching pattern (3); s3', electroplating the first under bump metal (4) and the interconnection hole chain test electrode (13) of the interconnection hole chain structure (14) by using the first under bump metal and the interconnection hole chain test electrode photoetching pattern (3) through electroplating liquid; s4', the first substrate (1) with the first under bump metal (4) and the interconnection hole chain test electrode (13) prepared is placed into acetone and absolute ethyl alcohol in sequence, photoresist is removed, and cleaning and drying are carried out; s5', spin-coating photoresist on the surface of the first substrate (1) after cleaning and drying, and photoetching a first metal bump photoetching pattern (5); S6', electroplating the first metal bump (6) of the interconnection hole chain structure (14) by using the first metal bump photoetching pattern (5) through electroplating solution; S7', sequentially placing the first substrate (1) with the first under bump metal (4) and the first metal bump (6) which are subjected to the preparation of the interconnection hole link structure (14) into acetone and absolute ethyl alcohol to remove photoresist, and cleaning and drying; S8', sequentially removing the exposed first electroplating seed layer (2) through a wet etching process or a dry etching process, wherein the removing sequence is opposite to the sputtering sequence, and cleaning and drying after etching is finished to prepare a first chip (15) to be bonded; S9', preparing a second chip (16) to be bonded by adopting the same steps as S1' to S8', in particular, preparing a second electroplating seed layer (9) on a second substrate (10) by adopting the same steps as S1' to S8', and preparing a second under bump metal (8) and a second metal bump (7) corresponding to the first under bump metal (4) and the first metal bump (6); S10' cleaning the prepared first chip (15) to be bonded and the second chip (16) to be bonded, then placing the cleaned chips into a hot press bonding machine or a flip-chip bonding machine with an alignment function, enabling the first under bump metal (4) and the first metal bump (6) to correspond to the second under bump metal (8) and the second metal bump (7) respectively, and completing bonding of the first chip (15) to be bonded and the second chip (16) to be bonded, thereby preparing and completing the micro bump bonding integrated chip interconnection hole chain structure.
  8. 8. The method for detecting the defect of the interconnection pore chain of the micro-bump bonding integrated chip according to claim 7, wherein, The first substrate (1) and the second substrate (10) are semiconductor single crystal substrates or epitaxial substrates, and the semiconductor material is any one or more of Si, gaAs, gaN, siC or InP.
  9. 9. The method for detecting the defect of the interconnection pore chain of the micro-bump bonding integrated chip according to claim 7, wherein, The plating seed layer metal of the first plating seed layer (2) and the second plating seed layer (9) is any one or more of Au, cu and Ni, and the thickness of the first plating seed layer (2) and the second plating seed layer (9) is not less than 50nm.
  10. 10. The method for detecting the defect of the interconnection pore chain of the micro-bump bonding integrated chip according to claim 7, wherein, And electroplating the first under-bump metal (4), the first metal bump (6), the second under-bump metal (8) and the second metal bump (7) by adopting direct current pulse or non-pulse, wherein the electroplated metal is Au, cu or Ni, and the bump thickness of the first under-bump metal (4), the first metal bump (6), the second under-bump metal (8) and the second metal bump (7) is not less than 500nm.

Description

Method for detecting and analyzing defects of interconnection hole chain of micro-bump bonding integrated chip Technical Field The application relates to the technical field of semiconductor processes, in particular to a method for detecting and analyzing defects of a micro-bump bonding integrated chip interconnection hole chain. Background Heterogeneous integration of semiconductor chips and 3D packaging technology have become key approaches for further miniaturization, weight reduction, multi-functionalization and intelligence of electronic components in the latter molar age. In the process of heterogeneous integration and advanced packaging technology, semiconductor chips are usually required to be interconnected and integrated in a micro bump bonding mode, and a plurality of semiconductor devices or chips are stacked and integrated in a vertical direction through an interconnection hole chain structure formed by metal micro bump bonding, so that the system volume and weight can be reduced, and the comprehensive performance can be improved. In recent years, as the volume of integrated chips is continuously reduced and the functions are continuously increased, the number of interconnection micro-bumps is continuously increased, and the area and the pitch (interconnection pitch) are continuously reduced. The interconnection hole chain structure is realized by micro-bump high-precision alignment bonding, and in the actual alignment bonding process, the failure of interconnection is often caused by alignment deviation caused by equipment or personnel operation or incorrect interconnection or poor bonding quality caused by immature bonding process conditions. In a narrow pitch interconnect pore chain structure composed of numerous micro-bumps, failure of a single micro-bump interconnect often results in failure of the entire integrated chip. Aiming at the failure of the integrated chip, the traditional analysis method needs to analyze the interconnection part of each micro bump in the bonding integrated interconnection hole chain structure one by one to find out the failure part, so that the failure analysis efficiency of the interconnection hole chain structure is low, and the production efficiency of the chip with the interconnection hole chain structure is affected. Therefore, there is a need for a method for efficiently detecting and analyzing interconnect hole chain defects in high density micro bump bonded integrated chips. Disclosure of Invention The application aims to provide a method for detecting and analyzing defects of a micro-bump bonding integrated chip interconnection hole chain, which can achieve the aim of analyzing the defects of the bonding integrated interconnection hole chain structure in batches by a way of polishing a cross section after scribing on the premise of completing preparation of the bonding integrated interconnection hole chain structure and confirming the abnormal electrical performance of the bonding integrated interconnection hole chain structure, and effectively improve the analysis efficiency of the bonding defects of the heterogeneous integration and advanced packaging integrated chip interconnection hole chain structure, thereby solving the problems mentioned in the background art. In order to achieve the purpose of the application, the following technical scheme is provided: The application provides a detection and analysis method of a micro-bump bonding integrated chip interconnection hole chain defect, wherein the micro-bump bonding integrated chip comprises a plurality of groups of interconnection hole chain structures, each group of interconnection hole chain structures is formed by bonding a first under-bump metal and a first metal bump which are positioned on a first chip to be bonded and a second under-bump metal and a second metal bump which are positioned on a second chip to be bonded, and both ends of each group of interconnection hole chain structures are respectively formed with interconnection hole chain test electrodes, and the detection and analysis method of the interconnection hole chain defect comprises the following steps: S1, performing direct-current electric test on each group of interconnected hole chain structures by using a direct-current detection probe platform through the interconnected hole chain test electrode, and judging and marking the interconnected hole chain structures with short circuits or open circuits according to data of the direct-current electric test; S2, utilizing a scribing device capable of positioning a scribing position to scribe a marked interconnection hole chain structure with short circuit or open circuit vertically downwards along the transverse central line of the interconnection hole chain structure from the top of the micro-bump bonding integrated chip so as to form a cross section of the interconnection hole chain structure; S3, polishing the cross section of the interconnection hole chain structure by using a