CN-122017711-A - Signal calibration method and system of semiconductor test equipment

CN122017711ACN 122017711 ACN122017711 ACN 122017711ACN-122017711-A

Abstract

The invention discloses a signal calibration method and a system of semiconductor test equipment, which relate to the technical field of semiconductor test and comprise the steps of selecting a calibration port, controlling a relay matrix to connect a source measurement channel, a time measurement channel and an electrical sensor into the same Kelvin terminal, transmitting a calibration pulse train, extracting a transmission segment, an arrival segment and a return segment, acquiring a port mirror image routing table and a baseline segment table, controlling the calibration pulse train to execute reversing transmission and polarity inversion along a corresponding path of the port mirror image routing table, comparing the arrival segment, the return segment and front and rear edge sequences to obtain a reversing difference table and a polarity adjustment code table, controlling the calibration pulse train to enter a tested branch and a reference straight-through branch respectively, and implementing single-stage trimming on a comparison decision chain and a delay unit chain. According to the invention, the measured branch is compared with the reference straight-through branch in parallel, and the comparison decision chain and the delay unit chain are subjected to step-by-step trimming, so that the measurement resolution of the time parameter is remarkably improved.

Inventors

LI WEIFANXING
ZHANG DELI
SHEN HONGXING
WANG CHAOQUN

Assignees

弘润半导体(苏州)有限公司

Dates

Publication Date: 20260512
Application Date: 20260409

Claims (10)

1. A signal calibration method of semiconductor test equipment is characterized by comprising the following steps of, Selecting a calibration port, controlling a relay matrix to connect a source measurement channel, a time measurement channel and an electrical sensor to the same Kelvin terminal, transmitting a calibration pulse train, extracting a transmitting segment, an arrival segment and a reflux segment, and acquiring a port mirror image routing table and a baseline segment table; Controlling the calibration pulse train to execute reversing transmission and polarity inversion along the corresponding path of the port mirror image routing table, and comparing the arrival segment, the backflow segment and the front and rear edge sequences to obtain a reversing difference table and a polarity setting code table; The calibration pulse train is controlled to enter a tested branch and a reference straight-through branch respectively, single-stage trimming is implemented on a comparison decision chain and a delay unit chain, a driving code, a decision chain trimming code and a time trimming code are determined, and a port execution code book is generated; The calling port executing code book applies a short pulse train to the pin to be tested, and verifies the sending segment, the arrival segment, the reflux segment and the front and rear edge sequences corresponding to the baseline segment list to obtain a real-time calling list; And establishing a port channel based on a real-time calling table, loading a driving code, a decision chain trimming code and a time trimming code, collecting voltage, current and time parameters, implementing amplitude trimming and time sequence trimming, and obtaining a signal calibration result.
2. The method for calibrating signals of semiconductor test equipment according to claim 1, wherein the step of connecting the source measurement channel, the time measurement channel and the electrical sensor to the same Kelvin terminal means that a special calibration port is selected, and the source measurement channel is connected to an excitation point of the Kelvin terminal, and the time measurement channel, the differential voltage sensor and the current sensor are connected to detection points of the Kelvin terminal through a relay matrix to generate a Kelvin terminal connection configuration table.
3. A signal calibration method for a semiconductor test apparatus according to claim 1, wherein said transmitting calibration pulse train comprises the steps of, The field programmable gate array sends out a calibration pulse train with a fixed form, and the calibration pulse train is divided into a front edge segment, a flat top segment and a rear edge segment in sequence to form a sending segment; And controlling the receiving end latch, the differential voltage sensor and the current sensor to synchronously latch the transmitting segment, the arrival segment and the reflux segment according to the calibration pulse train, so as to obtain a multi-segment synchronous latching data set.
4. The method for calibrating a signal of a semiconductor test apparatus according to claim 3, wherein the acquiring the port image routing table and the baseline segment table comprises the steps of, Extracting a sending segment, an arrival segment and a reflow segment corresponding to each physical path from the multi-segment synchronous latching data set to generate a baseline segment table; and recording the corresponding relation between the relay combination and the physical path according to the Kelvin terminal access configuration table, and generating a port mirror image routing table.
5. The method for calibrating a signal of a semiconductor test apparatus according to claim 4, wherein the obtaining the commutation difference table and the polarity setting table comprises the steps of, Calling a port mirror image routing table to switch a transmitting end and a receiving end of the same physical channel, and executing polarity inversion on the calibration pulse train to obtain all working condition fragments under the same physical channel; And comparing the corresponding arrival segment, the reflux segment and the front and rear edge sequences under each working condition, and extracting the path difference and the polarity difference to obtain a reversing difference table and a polarity setting code table.
6. The method for calibrating a signal of a semiconductor test apparatus according to claim 5, wherein the generating port performs a code book comprising the steps of, Invoking a reversing difference table and a polarity setting code table, sequentially gating and comparing a judging unit in a judging chain and a delay unit in a delay unit chain in a field programmable gate array, and distributing a calibration pulse train into a tested branch passing through a current unit and a reference straight-through branch bypassing the current unit; Enabling the forward segment and the reverse segment to sequentially pass through the detected branch and the reference straight-through branch, and comparing the arrival time deviation and the front and rear edge sequence of the two branches by the time measuring channel to determine the time sequence deviation of the current unit; adjusting the current unit according to the time sequence deviation until the forward segment and the reverse segment return to the same time sequence slot position on the tested branch and the reference straight-through branch to obtain a trimming result of the current unit; And collecting the trimming results of each current unit, determining a driving code, a decision chain trimming code and a time trimming code by combining a port mirror image routing table, a reversing difference table and a polarity setting code table, and generating a port execution code book.
7. The method for calibrating a signal of a semiconductor test apparatus according to claim 6, wherein said obtaining a real-time call table comprises the steps of, Extracting relay combinations, driving codes, decision chain trimming codes and time trimming codes corresponding to pins to be tested from a port execution code book, and applying a short pulse train to the pins to be tested to obtain verification fragments; and comparing the verification fragments with the sending fragments, the arrival fragments and the reflow fragments corresponding to the baseline fragment table, comparing the front and rear edge sequences of the verification fragments with time sequence slots corresponding to the time trimming codes, and reserving execution entries consistent in comparison to obtain the real-time calling table.
8. The method for calibrating a signal of a semiconductor test apparatus according to claim 7, wherein the establishing a port path based on the real-time calling table comprises the steps of, Extracting relay combination and switch closing sequences corresponding to pins to be tested according to a real-time calling table, and generating a channel establishment instruction; and sending a channel establishment instruction to the relay matrix, and switching on a source measurement channel, a time measurement channel, a differential voltage sensor and a current sensor to the pins to be tested to generate a test channel state.
9. The method for calibrating a signal of a semiconductor test apparatus according to claim 8, wherein the acquiring the signal calibration result comprises the steps of, Extracting a driving code, a decision chain trimming code, a time trimming code, a reversing difference table entry and a polarity setting code table entry from a real-time calling table, loading the driving code to a source measurement channel in a test path state, and loading the decision chain trimming code and the time trimming code to a time measurement channel; collecting voltage, current and time parameters, carrying out amplitude trimming according to commutation difference table entries and polarity setting code table entries, and carrying out time sequence trimming according to time trimming codes; And synthesizing the voltage value after the amplitude trimming, the current value after the amplitude trimming and the time value after the time sequence trimming to obtain a signal calibration result.
10. A signal calibration system of a semiconductor test apparatus based on the signal calibration method of the semiconductor test apparatus according to any one of claims 1 to 9, characterized by comprising, The port access module is used for selecting a calibration port, controlling the relay matrix to access the source measurement channel, the time measurement channel and the electrical sensor to the same Kelvin terminal, transmitting a calibration pulse train, extracting a transmitting segment, an arrival segment and a reflux segment, and acquiring a port mirror image routing table and a baseline segment table; The difference comparison module is used for controlling the calibration pulse train to execute reversing transmission and polarity inversion along the corresponding path of the port mirror image routing table, and comparing the arrival segment, the backflow segment and the front and rear edge sequences to obtain a reversing difference table and a polarity setting code table; The single-stage trimming module is used for controlling the calibration pulse train to enter the tested branch and the reference straight-through branch respectively, implementing single-stage trimming on the comparison judgment chain and the delay unit chain, determining a driving code, a judgment chain trimming code and a time trimming code, and generating a port execution code book; the verification calling module is used for calling the port execution code book to apply a short pulse train to the pin to be tested, verifying the sending segment, the arrival segment, the backflow segment and the front and rear edge sequence corresponding to the base line segment table, and obtaining a real-time calling table; The test execution module establishes a port passage based on the real-time calling table, loads a driving code, a decision chain trimming code and a time trimming code, acquires voltage, current and time parameters, implements amplitude trimming and time sequence trimming, and acquires a signal calibration result.

Description

Signal calibration method and system of semiconductor test equipment Technical Field The invention relates to the technical field of semiconductor testing, in particular to a signal calibration method and system of semiconductor testing equipment. Background Semiconductor test equipment is key equipment used for verifying the functions and performances of chips in the manufacturing process of integrated circuits, and the measurement accuracy directly influences the yield analysis and cost control of the chips. Along with the continuous evolution of the semiconductor process, the pin density of the chip is continuously increased, the signal rate is obviously improved, and higher requirements are put on the time parameter measurement precision and the voltage current output stability of the source measurement unit of the test equipment. Currently, mainstream semiconductor test equipment generally adopts a relay matrix to realize multi-pin multiplexing measurement, and channel gain, bias and time delay are regularly corrected through a built-in calibration source so as to maintain the metering characteristic of a test system. In the calibration process, the device generally injects standard signals into a specific path, and measurement errors are compensated through an algorithm after response is acquired, so that traceability of test results is guaranteed. However, existing calibration methods have significant limitations in dealing with complex test environments. The error sources in the test system have diversity, and the error sources comprise both path directivity errors introduced by sockets, connecting plates and relay contacts and circuit level errors introduced by inconsistent responses of a driving stage and a judging stage circuit to positive and negative polarity signals. The conventional calibration scheme generally carries out the error mixing processing, and corrects the measurement result by adopting an integral compensation mode, so that the channel error and the circuit error are mutually coupled and cannot be separated, and the stability of the calibration effect is difficult to ensure when the test condition changes. In addition, inter-stage timing sequence deviation of the comparison decision chain and the delay unit chain in the time measurement channel is often ignored or only adjusted integrally, so that fine single-stage trimming cannot be realized, and further improvement of time parameter measurement accuracy is limited. Disclosure of Invention The present invention has been made in view of the above-described problems occurring in the prior art. Therefore, the invention provides a signal calibration method of semiconductor test equipment, which solves the problems of insufficient signal calibration precision and poor time effectiveness of calibration results caused by mutual coupling of path directivity errors, circuit polarity asymmetry errors and internal time sequence deviations. In order to solve the technical problems, the invention provides the following technical scheme: In a first aspect, the present invention provides a signal calibration method for a semiconductor test apparatus, comprising, Selecting a calibration port, controlling a relay matrix to connect a source measurement channel, a time measurement channel and an electrical sensor to the same Kelvin terminal, transmitting a calibration pulse train, extracting a transmitting segment, an arrival segment and a reflux segment, and acquiring a port mirror image routing table and a baseline segment table; Controlling the calibration pulse train to execute reversing transmission and polarity inversion along the corresponding path of the port mirror image routing table, and comparing the arrival segment, the backflow segment and the front and rear edge sequences to obtain a reversing difference table and a polarity setting code table; The calibration pulse train is controlled to enter a tested branch and a reference straight-through branch respectively, single-stage trimming is implemented on a comparison decision chain and a delay unit chain, a driving code, a decision chain trimming code and a time trimming code are determined, and a port execution code book is generated; The calling port executing code book applies a short pulse train to the pin to be tested, and verifies the sending segment, the arrival segment, the reflux segment and the front and rear edge sequences corresponding to the baseline segment list to obtain a real-time calling list; And establishing a port channel based on a real-time calling table, loading a driving code, a decision chain trimming code and a time trimming code, collecting voltage, current and time parameters, implementing amplitude trimming and time sequence trimming, and obtaining a signal calibration result. The method for calibrating the signals of the semiconductor test equipment comprises the steps of selecting a special calibration port, connecting a source measurement channel, a ti