CN-122017791-A - Low-noise time quantization circuit suitable for laser radar focal plane detector

Abstract

The invention relates to a low-noise time quantization circuit suitable for a laser radar focal plane detector, and belongs to the technical field of laser radar focal plane detector readout circuits. Compared with the traditional TAC architecture, the invention utilizes the correlation of noise between the reset signal and the effective signal in the same pixel reading circuit based on the correlated double sampling principle, uses the pre-storage circuit in the pixel reading unit to buffer the reset voltage and the effective signal voltage, reads the difference to the correlated double sampling circuit through the column bus, greatly reduces the influence of noise such as 1/f noise, KCT noise, array fixed mode noise and the like, and improves the signal to noise ratio of focal plane imaging.

Inventors

• TIAN NA
• QIU MENGTING
• YUAN FEI
• SU HAIPENG
• KONG DEXUAN
• GUO CHANGDONG
• HAO XIN
• Ke zungui
• DENG SHIJIE
• FU JIARUI
• LI YUXIN
• QIU YUANMOU
• Yang Binxiu
• LIU WEI
• CAI YUSHAN
• XU JUNJIE
• LIU DINGQUAN

Assignees

• 西南技术物理研究所

Dates

Publication Date

20260512

Application Date

20251225

Claims (10)

1. 1. A low-noise time quantization circuit suitable for a laser radar focal plane detector is characterized by comprising an input logic unit, a time analog conversion circuit, a pre-storage circuit in a pixel unit, a column bus, a column parallel correlation double sampling circuit and an analog-to-digital conversion circuit, wherein the input logic unit is used for receiving a trigger signal TRG and a working enabling signal EXP_EN and correspondingly generating a conversion time gating signal GATE, the time analog conversion circuit comprises a timing capacitor C 0 and is used for converting the pulse width of the conversion time gating signal GATE into a voltage signal on the timing capacitor C 0 , the pre-storage circuit in the pixel unit is used for respectively storing a reset voltage V RST0 and an effective signal voltage V SIG0 on the timing capacitor C 0 , then the reset voltage V RST0 and the effective signal voltage V SIG0 are read out to the column parallel correlation double sampling circuit through the column bus, a voltage change value V RST0 -V SIG0 on the timing capacitor C 0 is obtained, and the analog-to-digital conversion circuit is further used for converting the output voltage of the column parallel correlation double sampling circuit into a digital signal D OUT and outputting the digital signal.
2. 2. The circuit as claimed in claim 1, wherein the input logic unit comprises a D flip-flop and an AND gate, the reset signal RSTN resets the input logic unit before starting operation, the trigger signal TRG is an avalanche pulse input signal, the avalanche pulse input signal TRG is connected to a clock port CK of the D flip-flop, an inverting output of the D flip-flop The input of the and GATE is connected to the operation enable signal exp_en, and the and GATE outputs the transition time GATE signal GATE.
3. 3. The circuit of claim 2, wherein the time analog conversion circuit is composed of a timing capacitor C 0 , a reset tube M RST0 , an adjustable current source I 0 and a switching tube NM 1 , wherein a reset signal RSTN is connected to the GATE of the reset tube M RST0 , a switching time GATE signal GATE is input to the GATE of the switching tube NM 1 , the source of the switching tube NM 1 is connected to one end of C 0 , the drain is connected to one end of I 0 , the other end is connected to the drain of M RST0 , and the other end of C 0 , and the timing capacitor C 0 is reset to a high level when the reset signal RSTN is at a low level.
4. 4. A circuit according to claim 3, wherein the pre-storage circuit in the pixel cell is formed by a source follower SF 1 , a bias current source I 1 , a current switch NM 2 , A transmission tube T 1 、T 2 、T 3 and a capacitor C 1 、C 2 , wherein the drain electrode of SF 1 is connected with the source electrode of M RST0 , the grid electrode is connected with the other end of C 0 , and the source electrode is connected with one end of I 1 , A T 1 collector, a NM 2 drain connected to the other end of I 1 , a NM 2 source grounded, a T 1 emitter connected to a T 3 collector, The collector of T 2 , the emitter of T 2 is connected with one end of C 1 , the other end of C 1 is grounded, the emitter of T 3 is connected with one end of C 2 , and the other end of C 2 is grounded.
5. 5. The circuit of claim 4, wherein the column bus is composed of a source follower SF 2 , a transmission tube T 4 and a column sharing current source I 2 , wherein the grid electrode of the source follower SF 2 is connected with the output of a pre-storage circuit in the pixel unit, namely a T 1 emitter, the source electrode of the source follower SF 2 is connected with the collector electrode of the T 4 , the emitter electrode of the T 4 is connected with one end of the I 2 and is used as the output of the column bus, the other end of the I 2 is grounded, and the output of the column bus is connected with the input of a column parallel related double sampling circuit.
6. 6. The circuit of claim 5, wherein the column-parallel correlated double sampling circuit comprises a switching tube T 5 ~ T 8 , a sampling capacitor C S 、C R and an operational amplifier, wherein the source electrode of T 5 is connected with one end of the I 2 , the drain electrode is connected with one end of C R , A source electrode of T 6 , a drain electrode of T 6 is connected with the first input end of the operational amplifier, a source electrode of T 7 is connected with one end of the I 2 , a drain electrode is connected with one end of C S , The source electrode of T 8 , the drain electrode of T 8 is connected with the second input end of the operational amplifier, the output end of the operational amplifier is the output end of the column parallel related double sampling circuit, the grid electrode of T 6 、T 8 is connected, and the other end of C S 、C R is grounded, a switching tube T 5 , The sampling capacitor C R samples the reset voltage V RST0 , the switching tube T 7 , The sampling capacitor C S samples the effective signal voltage V SIG0 , and the operational amplifier performs difference on the voltages of the two sampling capacitors after the switching tube T 6 、T 8 controlled by the signal F CDS of the grid electrode of T 8 is conducted, so as to obtain an effective signal V RST0 -V SIG0 .
7. 7. The circuit of claim 6, wherein the input of the analog-to-digital converter is connected to V RST0 -V SIG0 of the output of the column parallel correlated double sampling circuit and converts it to a digital signal D OUT for output.
8. 8. The circuit of claim 7 wherein the transmission tubes T 2 and T 3 are the same size and dimensions and the capacitors C 1 and C 2 are the same size and dimensions.
9. 9. A method of operating a circuit as claimed in claim 7 or 8, comprising the steps of: (1) A reset stage for resetting the D flip-flop by setting the reset signal RSTN to low level and the operation enable signal EXP_EN to low level before detection Simultaneously turning on a PMOS reset tube M RST0 to reset the timing capacitor C 0 to a high level voltage V RST0 , then setting a reset signal RSTN to a high level, turning off a signal EN 3 of a signal EN 1 、T 2 base of a signal EN 2 、NM 2 grid electrode of a base electrode of the reset tube M RST0 ;T 1 to a high level, sampling and storing the reset voltage on the timing capacitor C 0 by a capacitor C 1 through a source follower SF 1 , then restoring the low level by a control signal EN 3 , and turning off a transmission tube T 2 ; (2) The global detection stage comprises the steps of triggering a signal TRG to be low level initially, setting an operation enabling signal EXP_EN to be high level, inputting a switching time gating signal GATE in a logic unit to be high level, conducting a NM 1 pipe, discharging a timing capacitor C 0 through an adjustable current I 0 , triggering a D trigger to latch the high level by the rising edge of the signal TRG when a pixel front-end circuit detects a photon signal and correspondingly generates a high level pulse signal TRG, When EXP_EN turns to low level, the detection is ended, then the signal EN 4 of the base electrode of T 3 is set to high level, the capacitor C 2 samples and stores the voltage on the timing capacitor C 0 through the source follower SF 1 , the signal EN 4 is set to low level after the detection is finished, the signal of a closed transmission tube T 3 ;EN 1 is set to low level, and the bias current I 1 is closed; (3) The line pixel reading sampling stage comprises the steps of after global detection is finished, rolling line by line to read voltage signals on a capacitor C 1 、C 2 , setting a reset signal RSTN to be low level when the 1 st line pixel is read, setting a column bus transmission tube control signal EN 5 in the 1 st line pixel to be high level, conducting a T 4 tube, enabling a signal EN 5 in the other line pixels to keep low level, enabling a bias current source I 5 , pre-charging parasitic capacitance at an X point of a T 5 emitter through a source follower SF 5 and a transmission tube T 5 , sequentially setting the signal EN 5 to be low level, opening the transmission tube T 5 , setting a reset voltage signal V 5 stored on the capacitor C2 to be high level when a grid F 5 signal of the T 5 in a column parallel double-sampling circuit is set to be high level, conducting the signal EN 5 tube, setting the signal EN 5 in the capacitor C2 to be high level, pre-sampling the signal C 5 to be high level, sampling the parasitic capacitance at a pre-sampling point of the pre-sampling point, setting the signal EN 5 to be low level, sampling the pre-sampling signal EN 5 to be the parasitic capacitance at the pre-sampling point of the pre-sampling point, and then setting the pre-sampling point to be the parasitic capacitance to be the high level, and the pre-sampling point of the signal to be the pre-level to be the high level to the pre-level. The EN 4 、F S signal is set to be low level, the F CDS signal is set to be high level, and the related double sampling circuit performs difference on the voltage on the capacitor C R 、C S through a difference solving circuit formed by a switched capacitor amplifier to obtain an effective signal V RST0 -V SIG0 ; (4) The analog-to-digital conversion stage comprises an analog-to-digital conversion circuit converting a signal V RST0 -V SIG0 into a digital signal D OUT and outputting the digital signal to an off-chip or on-chip digital signal processing unit through a digital bus; (5) And (3) repeating the steps (3) and (4), driving a control signal EN 1 、EN 2 、EN 3 、EN 4 、EN 5 in the pixel array according to the row, and configuring a column parallel related double sampling circuit and an analog-digital conversion circuit according to a corresponding time sequence to realize signal reading and conversion of the whole pixel array.
10. 10. The method of claim 9, wherein the row select signal EN 5 at the base of signal F CDS 、T 4 is set low after the analog-to-digital conversion is completed.

Description

Low-noise time quantization circuit suitable for laser radar focal plane detector Technical Field The invention belongs to the technical field of laser radar focal plane detector readout circuits, and particularly relates to a low-noise time quantization circuit suitable for a laser radar focal plane detector. Background While traditional ammunition is low in manufacturing cost, but low in striking precision and cost effectiveness ratio, accurate guided weapons in modern weapons are high in precision and cost effectiveness ratio, and are receiving more and more attention in the field of weaponry. The laser radar focal plane detector has been successfully applied to modern accurate guided weapons at present, and has wide application prospects in aspects of fire control systems, target identification, trajectory interception and the like. The laser radar focal plane detector has the characteristics of long detection distance, rapid target capturing, high frame frequency and the like, can rapidly track various high-speed moving military targets, and provides reliable imaging data for a defense system. The laser radar focal plane detector usually adopts an avalanche diode (APD) as a front end detection device, wherein the APD focal plane detector can be divided into a linear mode APD and a Geiger mode APD according to the working state of the APD, the linear mode APD focal plane detector converts laser echo pulses into voltage pulse signals in a mode of a transimpedance amplifier (TIA) and a comparator, and the Geiger mode APD focal plane detector converts the laser echo pulses into the voltage pulse signals in a mode of a quenching circuit and a digital pulse shaping circuit (such as an inverter) and the like. In lidar focal plane detectors, where direct time of flight measurement is typically used to measure the distance of the reflector, three-dimensional imaging is achieved, time-to-digital (TDC) and time-to-analog (TAC) converters are two common time measurement circuits. The TDC circuit directly converts time information into digital information, has strong noise suppression capability and anti-interference performance, but has a complex structure, high power consumption and large layout area, and is usually realized in a mode of detecting based on a high-frequency clock or a multiphase clock, the high-frequency clock overturn can cause serious interference to power supply and ground signals, and in a linear mode APD focal plane detector, the high-frequency power supply ground noise can cause serious interference to analog circuits such as TIA, a comparator and the like, so that the detection performance is reduced. Compared with a time-digital conversion circuit, the circuit based on the time-analog conversion method avoids a large number of digital units from being used, does not need high-frequency or multiphase clock signals, has the area and power consumption far smaller than those of a TDC circuit, is beneficial to improving the filling factor of pixel units, and in addition, in a linear mode APD focal plane detector, a TAC circuit does not cause excessive interference on power ground signals, so that the requirements of analog front-end circuits such as TIA, comparators and the like on the power supply rejection ratio are reduced, and the overall signal-to-noise ratio of the pixel front-end circuit is beneficial to improvement. However, the TAC circuit also has some problems, firstly, the analog voltage signal generated by the TAC circuit is easily interfered by 1/f noise, KCT noise and the like, and secondly, the wiring error on the analog readout bus, the threshold voltage deviation of the source follower in the pixel readout circuit and the like can further cause fixed mode noise, so that the signal-to-noise ratio of array imaging is reduced. How to realize low-noise time quantization and readout of a laser radar focal plane detector based on a TAC circuit is a technical problem to be solved urgently. Disclosure of Invention First, the technical problem to be solved The invention aims to solve the technical problem of providing a low-noise time quantization circuit suitable for a laser radar focal plane detector, which is used for solving the requirements of small size, low noise and low power consumption of a large-array focal plane detector. (II) technical scheme In order to solve the technical problems, the invention provides a low-noise time quantization circuit suitable for a laser radar focal plane detector, which comprises an input logic unit, a time analog conversion circuit, a pre-storage circuit in a pixel unit, a column bus, a column parallel related double sampling circuit and an analog-to-digital conversion circuit, wherein the input logic unit is used for receiving a trigger signal TRG and a working enabling signal EXP_EN and correspondingly generating a conversion time gating signal GATE, the time analog conversion circuit comprises a timing capacitor C 0 and is used for convertin