CN-122018085-A - Silicon optical chip, wafer and testing method

CN122018085ACN 122018085 ACN122018085 ACN 122018085ACN-122018085-A

Abstract

The invention relates to a silicon optical chip, wherein an optical waveguide inlet and an optical waveguide outlet are arranged on the side surface of a first side, a plurality of DC bonding pads are arranged on the upper surface of a second side, a plurality of RF bonding pads are arranged on the upper surface of a third side, a groove for an optical probe to enter is arranged on the edge of the upper surface of a fourth side, the groove is lower than the optical waveguide inlet and the optical waveguide outlet, and the optical waveguide inlet and the optical waveguide outlet are in the coverage range when the groove rotates anticlockwise by 90 degrees. The wafer comprises four silicon optical chips which are arranged in an array mode in a plurality of rows and a plurality of columns, wherein the four silicon optical chips in each group are distributed in a rotating mode around the center, the light inlet waveguide and the light outlet waveguide of one silicon optical chip in two adjacent silicon optical chips are opposite to the grooves of the other silicon optical chip, and cutting channels are arranged between the two adjacent silicon optical chips and between the two adjacent silicon optical chips. The wafer waste area is effectively reduced, the wafer area utilization rate is maximized, and the cost is reduced.

Inventors

FANG WENYIN
Shou Huiqiang
FU CHANG
YANG KUI
YAN XIONGWU
PENG KAISHENG

Assignees

武汉钧恒科技有限公司

Dates

Publication Date: 20260512
Application Date: 20251219

Claims (10)

1. A silicon optical chip, characterized in that it is rectangular, having four sides in clockwise order, a first side, a second side, a third side and a fourth side, the first side having an optical waveguide (110) and an optical waveguide (120) on its side, the second side having a plurality of DC pads (130), the third side having a plurality of RF pads (140), the fourth side having a groove (150) on its upper surface edge for the entry of an optical probe for testing and coupling into the optical waveguide (110) and out of the optical waveguide (120), the groove (150) being lower than the optical waveguide (110) and out of the optical waveguide (120), the groove (150) being within its coverage when rotated 90 ° counterclockwise into the optical waveguide (110) and out of the optical waveguide (120).
2. The silicon photonics chip of claim 1 wherein the trench (150) has a width of 100 μm to 120 μm and a depth of 100 μm to 120 μm.
3. A silicon photonics chip of claim 2 wherein the trench (150) has a width of 100 μm and a depth of 100 μm.
4. A silicon photonics chip in accordance with claim 1 in which the trench (150) is etched using a laser grooving technique.
5. A silicon photonics chip in accordance with any of claims 1-4 in which the light-entering waveguide (110) is distributed obliquely.
6. The silicon photonics chip of any one of claims 1-5 wherein the light-out waveguide (120) is obliquely distributed.
7. The silicon optical chip according to any one of claims 1 to 6, wherein the number of the light-entering waveguides (110) is one, the number of the light-exiting waveguides (120) is four, and the light-entering waveguides (110) are respectively coupled with the four light-exiting waveguides (120).
8. The wafer is characterized by comprising a plurality of silicon optical chips (1) as claimed in any one of claims 1-7, wherein all the silicon optical chips (1) are distributed in an array mode of a plurality of rows and a plurality of columns in a group of four, the four silicon optical chips (1) in each group are distributed in a rotating mode around the center, the light inlet waveguide (110) and the light outlet waveguide (120) of one silicon optical chip (1) in the adjacent two silicon optical chips (1) are opposite to the grooves (150) of the other silicon optical chip (1), and cutting channels (2) are formed between the adjacent two columns of silicon optical chips (1) and between the adjacent two rows of silicon optical chips (1).
9. A wafer according to claim 8, characterized in that the width of the scribe line (2) is 15 μm.
10. A wafer testing method according to claim 8 or 9, comprising the step of allowing a plurality of optical probes to enter the grooves (150) of the same silicon optical chip (1) and to couple with the light-in waveguide (110) and the light-out waveguide (120) of the silicon optical chip (1), respectively, so as to perform the photoelectric performance test.

Description

Silicon optical chip, wafer and testing method Technical Field The invention relates to the technical field of chips, in particular to a silicon optical chip, a wafer and a testing method. Background The silicon optical chip generally adopts side light-in and light-out, the specific structure is shown in fig. 1, the silicon optical chip is rectangular, four sides are a first side, a second side, a third side and a fourth side in turn along the clockwise direction, the side of the first side is provided with an light-in waveguide and a light-out waveguide, the light-in waveguide is coupled with the light-out waveguide, the upper surface of the second side is provided with a plurality of DC bonding pads, the upper surface of the third side is provided with a plurality of RF bonding pads, and the fourth side is a blank place. When silicon photonics chips of this type are mass-produced on wafers, they have 2 layout forms, respectively as follows: 1) All silicon optical chips are in the same direction and are distributed in an array mode in a plurality of rows and columns, cutting channels are arranged between two adjacent columns of silicon optical chips, the width of each cutting channel is 15 mu m, the current wafer-level photoelectric performance test of the silicon optical chips (see patent document with the application number 2022106665713 in particular) requires that photoetching grooves which are convenient for testing optical probes are etched between two adjacent rows of silicon optical chips, the width of each photoetching groove can be 100 mu m, and the depth of each photoetching groove can be 100 mu m, wherein the first side of each silicon optical chip faces towards the corresponding photoetching groove, the mode wastes the effective area of a wafer, particularly a 12-inch wafer, and the area with the width of 7 rows of 100 mu m is wasted in the mode, namely, the mode is shown in figure 2, wherein the silicon optical chips with 8 rows and 8 columns of silicon optical chips are taken as an example; 2) All silicon optical chips are distributed in an array mode in a plurality of rows and columns, cutting channels are arranged between every two adjacent columns of silicon optical chips, the width of each cutting channel is 15 mu m, all silicon optical chips are in a group in 2 rows, the first side of the silicon optical chip in the previous row is close to the first side of the silicon optical chip in the next row, namely, the light inlet waveguide of the silicon optical chip in the previous row and the light outlet waveguide of the silicon optical chip in the next row are close to the light inlet waveguide and the light outlet waveguide of the silicon optical chip in the next row, the wafer-level photoelectric performance test of the current silicon optical chip requires etching a photoetching groove between the two silicon optical chips in the same group for optical probe test, the width of each photoetching groove can be 100 mu m, the depth of each photoetching groove can be 100 mu m, the first side of each silicon optical chip is close to the corresponding to the photoetching groove, even if the silicon optical chip in the previous row is in the group in 2 rows and is close to the layout, the wafer area is wasted, and the wafer has 8 rows of silicon optical chips in the next row in the mode, and the area with the width of 4 rows being 100 mu m is wasted. Disclosure of Invention The invention aims to provide a silicon optical chip, a wafer and a testing method, which are used for overcoming the defects in the prior art. The technical scheme for solving the technical problems is as follows: A silicon optical chip is rectangular, four sides are a first side, a second side, a third side and a fourth side in turn along the clockwise direction, an optical waveguide inlet and an optical waveguide outlet are arranged on the side face of the first side, a plurality of DC bonding pads are arranged on the upper surface of the second side, a plurality of RF bonding pads are arranged on the upper surface of the third side, a groove for a probe for testing and coupling the optical waveguide inlet and the optical waveguide outlet is arranged on the edge of the upper surface of the fourth side, the groove is lower than the optical waveguide inlet and the optical waveguide outlet, and the optical waveguide inlet and the optical waveguide outlet are in the coverage range when the groove rotates anticlockwise by 90 degrees. The beneficial effects of the invention are as follows: When the silicon optical chips are produced on the wafer in batch, all the silicon optical chips can be distributed in a mode of a plurality of rows and columns in a group of four, the four silicon optical chips in each group are distributed in a rotating mode around the center, the light-in waveguide and the light-out waveguide of one of the adjacent two silicon optical chips are opposite to the groove of the other silicon optical chip, cutt