CN-122018228-A - Mask plate and layout generation method

CN122018228ACN 122018228 ACN122018228 ACN 122018228ACN-122018228-A

Abstract

The application discloses a mask plate and a layout generation method, wherein the pattern formed on the mask plate comprises a main pattern, a first alignment pattern and a second alignment pattern, wherein the main pattern is used for forming a target structure, the target structure is a structure in a semiconductor device product, the main pattern is formed in a central area of the mask plate, the first alignment pattern is formed in a first edge area of the mask plate, the first edge area is positioned on one side of the central area along a longitudinal axis direction, the second alignment pattern is formed in a second edge area of the mask plate, the second edge area is positioned on the other side of the central area along the longitudinal axis direction, the first alignment pattern and the second alignment pattern are identical in shape, and the abscissa of the first alignment pattern and the abscissa of the second alignment pattern are identical. The application can offset the exposure pattern offset generated by the thermal expansion of the mask plate by forming the alignment patterns with the same shape and the same abscissa in the two edge regions of the mask plate along the longitudinal axis direction.

Inventors

YANG HONGMEI
DONG JUN
XIA YIN
JIN PEI
JU BIYU
ZHANG QIXUE

Assignees

华虹半导体(无锡)有限公司
华虹半导体制造(无锡)有限公司

Dates

Publication Date: 20260512
Application Date: 20260121

Claims (6)

1. A mask blank, wherein a pattern formed on the mask blank comprises: A main pattern for forming a target structure, the target structure being a structure in a semiconductor device product, the main pattern being formed in a central region of the mask, the central region being a rectangular region centered on a center of the mask, a length of the central region being smaller than a length of the mask, a width of the central region being smaller than a width of the mask; A first alignment pattern formed in a first edge region of the mask plate, the first edge region being located at one side of the central region in a longitudinal axis direction; and the second alignment pattern is formed in a second edge area of the mask plate, the second edge area is positioned on the other side of the central area along the longitudinal axis direction, the first alignment pattern and the second alignment pattern have the same shape, and the abscissa of the first alignment pattern and the abscissa of the second alignment pattern are the same.
2. The mask plate according to claim 1, wherein when exposure is performed using the mask plate, alignment is performed by the first alignment pattern and the second alignment pattern to cancel an exposure pattern shift of the mask plate due to thermal expansion.
3. The reticle of claim 2, wherein a first distance between the first alignment pattern and a side length of its nearest reticle along the longitudinal axis and a second distance between the second alignment pattern and a side length of its nearest reticle along the longitudinal axis are equal.
4. The layout generation method is characterized by comprising the following steps: Inserting a main pattern into a central area, wherein the main pattern is used for forming a target structure, the target structure is a structure in a semiconductor device product, the central area is a rectangular area taking the center of a layout as the center, the length of the central area is smaller than the length of the layout, and the width of the central area is smaller than the width of the layout; Inserting a first alignment pattern into a first edge region, the first edge region being located on one side of the central region in a longitudinal axis direction; inserting a second alignment pattern into a second edge region, wherein the second edge region is positioned on the other side of the central region along the longitudinal axis direction, the first alignment pattern is identical to the second alignment pattern in shape, and the abscissa of the first alignment pattern is identical to the abscissa of the second alignment pattern.
5. The method of claim 4, wherein inserting the second alignment pattern into the second edge region comprises: Acquiring the abscissa of the first alignment graph; the second alignment pattern is inserted into the second edge region and the abscissa of the second alignment pattern is made identical to the abscissa of the first alignment pattern.
6. The method of claim 5, wherein a first distance between the first alignment pattern and the side length of its nearest layout along the longitudinal axis is equal to a second distance between the second alignment pattern and the side length of its nearest layout along the longitudinal axis.

Description

Mask plate and layout generation method Technical Field The application relates to the technical field of semiconductor devices and integrated circuits, in particular to a mask plate and a layout generation method. Background In the fabrication of semiconductor devices, it is often necessary to form a plurality of thin film layers stacked one above the other and to form a desired pattern in the corresponding thin film layers. When the current thin film layer is subjected to a photolithography process, alignment patterns (ALIGNMENT MARK) in the current thin film layer and alignment patterns formed in the previous thin film layer need to be aligned so that the patterns in the current thin film layer are formed at target positions. In practical applications, various errors may cause a deviation between a pattern formed in a photolithography process and a target position, resulting in overlay error (OVL). Overlay error measurement (OVL measurement) is an important means of monitoring alignment accuracy in photolithography processes due to the presence of overlay errors. The overlay error is affected by various factors, whether the overlay error measurement is large or small, and when the overlay error is stable, the desired exposure effect can be obtained by compensating the advanced process control (advanced process control, APC) system. However, when a mask (also called a "mask") is subject to deformation due to thermal expansion after an excessively long exposure time, especially when the mask has a low transmittance (clear ratio), the exposure energy is high and the exposure times are too high, the overlay error measurement value of the wafers in the same lot will show a tendency to drop or rise as a whole, and the difference between the wafers is large, which is difficult to compensate effectively by the system. In view of the foregoing, it is desirable to provide a mask plate capable of reducing the problem of larger overlay error deviation caused by excessively long exposure time. Disclosure of Invention The application provides a mask plate and a layout generation method, which can solve the problem of large overlay error caused by overlong exposure time of the mask plate in the related technology. In one aspect, an embodiment of the present application provides a mask, where a pattern formed on the mask includes: A main pattern for forming a target structure, the target structure being a structure in a semiconductor device product, the main pattern being formed in a central region of the mask, the central region being a rectangular region centered on a center of the mask, a length of the central region being smaller than a length of the mask, a width of the central region being smaller than a width of the mask; A first alignment pattern formed in a first edge region of the mask plate, the first edge region being located at one side of the central region in a longitudinal axis direction; and the second alignment pattern is formed in a second edge area of the mask plate, the second edge area is positioned on the other side of the central area along the longitudinal axis direction, the first alignment pattern and the second alignment pattern have the same shape, and the abscissa of the first alignment pattern and the abscissa of the second alignment pattern are the same. In some embodiments, when the mask plate is used for exposure, alignment is performed by the first alignment pattern and the second alignment pattern to offset exposure pattern shift of the mask plate due to thermal expansion. In some embodiments, the first distance is equal to the second distance, the first distance being the distance between the first alignment pattern and its nearest side of the reticle along the longitudinal axis, and the second distance being the distance between the second alignment pattern and its nearest side of the reticle along the longitudinal axis. On the other hand, the embodiment of the application provides a layout generation method, which comprises the following steps: Inserting a main pattern into a central area, wherein the main pattern is used for forming a target structure, the target structure is a structure in a semiconductor device product, the central area is a rectangular area taking the center of a layout as the center, the length of the central area is smaller than the length of the layout, and the width of the central area is smaller than the width of the layout; Inserting a first alignment pattern into a first edge region, the first edge region being located on one side of the central region in a longitudinal axis direction; inserting a second alignment pattern into a second edge region, wherein the second edge region is positioned on the other side of the central region along the longitudinal axis direction, the first alignment pattern is identical to the second alignment pattern in shape, and the abscissa of the first alignment pattern is identical to the abscissa of the second alignment pat