CN-122018252-A - Semiconductor layout processing method and related product

CN122018252ACN 122018252 ACN122018252 ACN 122018252ACN-122018252-A

Abstract

The invention provides a semiconductor layout processing method and related products. The method comprises the steps of obtaining a correction target edge on a semiconductor layout, breaking the correction target edge for the first time according to a preset length, carrying out primary optical proximity effect correction on the correction target edge to obtain a primary optimization edge corresponding to the correction target edge, obtaining a target line segment from the primary optimization edge according to the distance between the primary optimization edge and the correction target edge, determining a breaking position on the correction target edge according to the target line segment and a process limiting length, wherein the process limiting length is larger than the preset length, carrying out secondary breaking on the correction target edge according to the breaking position, and carrying out secondary optical proximity effect correction on the correction target edge. The scheme of the invention eliminates the result difference caused by different engineers, can adaptively cover any graphic scene such as corners, ends, straight line sections and the like, and rapidly outputs the optimized result meeting the inspection of mask rules.

Inventors

HUANG JIE

Assignees

深圳晶源信息技术有限公司

Dates

Publication Date: 20260512
Application Date: 20260402

Claims (10)

1. A semiconductor layout processing method, comprising: Acquiring a correction target edge on the semiconductor layout; breaking the correction target edge for one time according to a preset length, and correcting the correction target edge for one time by using an optical proximity effect to obtain a preliminary optimization edge corresponding to the correction target edge; acquiring a target line segment from the preliminary optimized edge according to the distance between the preliminary optimized edge and the correction target edge; Determining the breaking position on the corrected target edge according to the target line segment and the process limiting length, wherein the process limiting length is larger than the preset length; and performing secondary interruption on the correction target side according to the interruption position, and performing secondary optical proximity effect correction on the correction target side.
2. The semiconductor layout processing method according to claim 1, wherein, The obtaining a target line segment from the preliminary optimized edge according to the distance between the preliminary optimized edge and the correction target edge comprises the following steps: dividing the preliminary optimized edge based on the intersection point of the preliminary optimized edge and the correction target edge to obtain an initial separation section; Determining a line segment parallel to a line segment corresponding to the correction target edge in each line segment in the initial separation segment to obtain a parallel line segment; obtaining the distance between each parallel line segment and the corresponding position on the correction target side; And taking the parallel line segment corresponding to the maximum distance as the target line segment.
3. The semiconductor layout processing method according to claim 1, wherein, The determining the breaking position on the modified target edge according to the target line segment and the process limiting length comprises the following steps: Determining a mapping line segment corresponding to the target line segment and a connecting line segment connected with the mapping line segment on the correction target edge; comparing the length of the mapping line segment with the process limiting length, and extending or eliminating the mapping line segment with the length smaller than the process limiting length; Comparing the length of the connecting line segment with the process limiting length, and eliminating the connecting line segment with the length smaller than the process limiting length; Taking the end points of the processed mapping line segments and the end points of the processed connecting line segments as a first group of breaking positions, determining a second group of breaking positions on each processed mapping line segment according to the process limiting length, and determining a third group of breaking positions on each processed connecting line segment according to the process limiting length; the break locations include a first set of the break locations, a second set of the break locations, and a third set of the break locations.
4. A semiconductor layout processing method according to claim 3, wherein, The extending or eliminating treatment of the mapping line segment with the length smaller than the process limit length comprises the following steps: Obtaining a mapping line segment with the length smaller than the process limiting length and the total length of the connecting line segment connected with the mapping line segment; determining an end point of the mapping line segment on at least one of the connecting line segments connected to the mapping line segment when the total length is greater than or equal to the process-defined length, so that the length of the mapping line segment is equal to the process-defined length; and when the total length is smaller than the process limiting length, taking the midpoint of the mapping line segment as the endpoint of the connecting line segment connected with the mapping line segment so as to eliminate the mapping line segment.
5. The semiconductor layout processing method according to claim 4, wherein, Said determining an end point of said mapped line segment on at least one of said connecting line segments connected to said mapped line segment comprises: When the sum of the lengths of the mapping line segment and each connecting line segment connected with the mapping line segment is smaller than or equal to the process limiting length, taking the end point of the connecting line segment with a shorter length, which is far away from the mapping line segment, as the end point of the mapping line segment so as to eliminate the connecting line segment; when the sum of the lengths of the mapping line segment and one connecting line segment connected with the mapping line segment is smaller than or equal to the process limiting length, taking the end point of the connecting line segment far away from the mapping line segment as the end point of the mapping line segment so as to eliminate the connecting line segment; When the sum of the lengths of the mapping line segment and each connecting line segment connected with the mapping line segment is larger than the process limiting length, the end point of the mapping line segment is determined only on the connecting line segment with longer length, or the end point of the mapping line segment is determined on two connecting line segments, and the ratio between the eliminated part lengths on the two connecting line segments is equal to the ratio between the lengths of the two connecting line segments.
6. A semiconductor layout processing method according to claim 3, wherein, The elimination processing of the connecting line segment with the length smaller than the process limit length comprises the following steps: Identifying whether an intersection point exists between the preliminary optimized edge and a connecting line segment with the length smaller than the length limited by the process; when an intersection point exists between the preliminary optimization edge and the connecting line segment, the intersection point is used as the end point of the mapping line segment or the connecting line segment connected with the connecting line segment so as to eliminate the connecting line segment; And when no intersection point exists between the preliminary optimization edge and the connecting line segment, taking the midpoint of the connecting line segment as the end point of the mapping line segment or the connecting line segment connected with the connecting line segment so as to eliminate the connecting line segment.
7. A semiconductor layout processing method according to claim 3, wherein, Said determining a second set of said break locations on each of said mapped line segments after processing according to said process defined length comprising: when the length of the mapping line segment is greater than or equal to 2 times of the process limiting length, equally dividing the mapping line segment, wherein the length of each segment after equally dividing the mapping line segment is greater than or equal to the process limiting length and is less than 1.5 times of the process limiting length; Taking the equipartition position on the mapping line segment as a second group of breaking positions; said determining a third set of said break locations on each of said processed connection line segments according to said process defined length comprising: When the length of the connecting line segment is more than or equal to 2 times of the process limiting length, equally dividing the connecting line segment, wherein the length of each segment after equally dividing the connecting line segment is more than or equal to the process limiting length and less than 1.5 times of the process limiting length; And taking the equipartition position on the connecting line segment as a third group of breaking positions.
8. The semiconductor layout processing method according to claim 1, wherein, The obtaining the correction target edge on the semiconductor layout comprises the following steps: performing optical proximity effect correction on the semiconductor layout to obtain a correction pattern; Acquiring a weak point pattern or a dead point pattern from the corrected pattern; And determining the correction target edge according to the weak point pattern or the bad point pattern.
9. A computer readable storage medium having stored thereon a computer program, which when executed by a processor, implements the steps of the semiconductor layout processing method of any of claims 1 to 8.
10. A computer program product comprising a computer program which, when executed by a processor, implements the steps of the semiconductor layout processing method of any of claims 1 to 8.

Description

Semiconductor layout processing method and related product Technical Field The invention relates to a semiconductor layout processing technology, in particular to a semiconductor layout processing method and related products. Background In the field of semiconductor fabrication, optical proximity correction (OPC, optical proximity correction) has become essential starting from the 180nm technology node, where the minimum linewidth on the semiconductor device starts to be smaller than the exposure wavelength. The pattern on the reticle is projected onto the photoresist by the exposure system, and the pattern on the photoresist and the pattern on the mask are not completely consistent due to imperfections and diffraction effects of the optical system. The optical proximity correction is to correct the pattern on the mask by using a calculation method, so that the pattern projected onto the photoresist meets the design requirement as much as possible. The goal of OPC correction is to make the exposure pattern and the design pattern coincide, specifically the edge placement Error (EPE, edge Placement Error) is within an acceptable range, and OPC correction requires Mask Rule Check (MRC) to determine if the constraints of the relevant manufacturing rules are met. Such as minimum line width, line spacing, spacing between pattern corners, etc. For very long lines in OPC correction, it is generally considered to break into relatively short lines to obtain more variables for optimization so that better optimization results can be obtained. Different breaking modes bring about different correction results. Firstly, performing initial breaking on an input layout, performing OPC optimization on the processed layout, performing photoetching rule checking (LRC, lithography Rule Check) to find out bad points, adjusting breaking variables nearby the bad points, performing OPC optimization and performing LRC checking, and if the breaking variables nearby the bad points cannot be solved, adjusting breaking variables nearby the bad points again until the bad points are solved. However, the current OPC optimization flow has some problems such as strong experience dependence and insufficient scheme coverage, the existing scheme is highly dependent on experience judgment of OPC engineers, and the scheme is difficult to systematically cover all potential scenes due to the fact that the possibility of combination of interruption is almost infinite and the solution optimizing process has large contingency, so that the scheme adaptation coverage is low. The execution efficiency is lagged, the production aging requirement cannot be met, the scheme has a longer landing period, and a relatively ideal optimization result can be output only by 1 to 2 weeks aiming at the typical defect problem. However, the production site has strict aging requirement on abnormal response, generally requires closed loop within one week, and the existing OPC optimization process has obvious problem on time adaptability. Disclosure of Invention In view of the above problems, the present invention is provided to provide a semiconductor layout processing method and related products for overcoming the above problems or at least partially solving the above problems, so as to solve the problems of the existing optimizing process that the scheme adaptation coverage rate is low due to the fact that the existing optimizing process is relatively accidental and all potential scenes are difficult to systematically cover, and solve the problems that the execution efficiency is lagged, the production aging requirement cannot be met, and the scheme landing period is relatively long. According to one aspect of the present invention, there is provided a semiconductor layout processing method, comprising: Acquiring a correction target edge on the semiconductor layout; breaking the correction target edge for one time according to a preset length, and correcting the correction target edge for one time by using an optical proximity effect to obtain a preliminary optimization edge corresponding to the correction target edge; acquiring a target line segment from the preliminary optimized edge according to the distance between the preliminary optimized edge and the correction target edge; Determining the breaking position on the corrected target edge according to the target line segment and the process limiting length, wherein the process limiting length is larger than the preset length; and performing secondary interruption on the correction target side according to the interruption position, and performing secondary optical proximity effect correction on the correction target side. Optionally, the obtaining a target line segment from the preliminary optimized edge according to the distance between the preliminary optimized edge and the correction target edge includes: dividing the preliminary optimized edge based on the intersection point of the preliminary optimized edge and t