CN-122018277-A - Double-edge time-to-digital converter, time domain memory circuit and CIM chip

CN122018277ACN 122018277 ACN122018277 ACN 122018277ACN-122018277-A

Abstract

The invention belongs to the field of integrated circuits, and particularly relates to a double-edge time-to-digital converter, a time domain memory circuit and a CIM chip. The TDC comprises a symbol judging module and a numerical value calculating module, wherein the symbol judging module is used for respectively quantizing the values of symbol bits of a first calculation result corresponding to the rising edge and a second calculation result corresponding to the falling edge according to an input calculation signal A and a reference signal B. The numerical value calculation module comprises a shaping unit, a first delay chain, a second delay chain, a quantization unit, a transcoding unit and a separation storage unit. Shaping A and B to obtain or signal C and AND signal D. And obtaining thermometer codes of numerical digits of two calculation results according to C and D through exclusive OR operation of gradient delay and quantization units of the two delay chains, and finally completing data transcoding and extraction of asynchronous calculation results through a transcoding unit and a separation storage unit. The invention solves the problem of higher area and power consumption of the existing circuit.

Inventors

LIN ZHITING
WANG JIE
LIU YANCHUN
DU YUMENG
DUAN CHENGLONG
DAI CHENGHU
LIU YU
LI XIN
WU XIULONG

Assignees

安徽大学

Dates

Publication Date: 20260512
Application Date: 20260410

Claims (10)

1. A double edge time to digital converter, comprising: the symbol judgment module is used for respectively quantizing the values of symbol bits of a first calculation result corresponding to the rising edge and a second calculation result corresponding to the falling edge according to the input calculation signal A and the reference signal B; the numerical value calculation module comprises a shaping unit, a first delay chain, a second delay chain, a quantization unit, a transcoding unit and a separation storage unit, wherein the shaping unit is used for carrying out OR operation and AND operation on A and B respectively to obtain OR signals C and AND signals D, the first delay chain adopts n adjustable delay units to generate n delay signals C1-Cn with unit delay intervals in sequence according to the input C, the second delay chain adopts n fixed delay units to generate n delay signals D1-Dn with intrinsic delay intervals in sequence according to the input D, the quantization unit comprises n exclusive OR gates, two input ends of the ith exclusive OR gate are respectively connected with signals Ci and Di output by an ith stage in the first delay chain and the second delay chain, the output end outputs values of i=1-n of thermometer codes representing the first calculation result or the second calculation result, the transcoding unit is used for converting the thermometer codes of the n bits output by the quantization unit into m binary codes, 2= 2 m , and the quantization unit comprises n exclusive OR gates, and the two input ends of the ith exclusive OR gates are respectively connected with the output ends of the ith exclusive OR gates in the second delay chain and the second delay chain respectively to realize the calculation result and the output of the first calculation result and the second calculation result through the D.
2. The double edge time-to-digital converter of claim 1, wherein the fixed delay unit and the adjustable delay unit adopt the same delay circuit, the delay circuit comprises 3 PMOS tubes P1-P3 and 3 NMOS tubes N1-N3, the sources of P1 and P3 are connected with VDD, the drains of P1 are connected with the sources of P2, the drains of P2 and N2 are connected with the gates of P3 and N3, the sources of N2 are connected with the drains of N1, the sources of N1 and N3 are connected with VSS, the gates of P2 and N2 are connected and serve as input ends IN of the delay circuit, and the drains of P3 and N3 are connected and serve as output ends OUT of the delay circuit; In the fixed delay unit, the grid electrode of N1 is connected with VDD, and the grid electrode of P1 is connected with VSS; in the adjustable delay unit, the gate of N1 is connected to the first BIAS voltage BIAS1, and the gate of P1 is connected to the second BIAS voltage BIAS2.
3. The double edge time-to-digital converter of claim 2 wherein the quantization accuracy and range of said numerical calculation module are adjusted by adjusting the voltage values of BIAS1 and BIAS2 to change the length of the unit delay generated by each stage of adjustable delay unit in the first delay chain.
4. The double edge time-to-digital converter of claim 1 wherein said fixed delay element and said adjustable delay element are different delay circuits.
5. The double edge time to digital converter of claim 1 wherein the range of said numerical computation module is adjusted by adjusting the number of delay elements in said first and second delay chains and the number n of input bits of the transcoding element.
6. The double edge time-to-digital converter of claim 1 wherein said shaping unit comprises an OR gate OR0 AND an AND gate AND0, wherein the OR0 has two inputs connected to A AND B, respectively, an output for outputting OR signal C, AND the AND0 has two inputs connected to A AND B, respectively, an output for outputting AND signal D.
7. The double edge time-to-digital converter of claim 1 wherein said separate storage unit comprises 2m D flip-flops, wherein m D flip-flops comprise a first register unit; In the first register unit, the data input end of each D trigger is respectively connected with the 1 st to the m th bits of the binary code output by the transcoding unit and is marked as F1 to Fm; In the second register unit, the data input end of each D trigger is respectively connected with the 1 st to the m th bits of the binary code output by the transcoding unit and is marked as F1-Fm, the clock input end is used for connecting with the OR signal C, and the data output end is used for outputting the 1 st to the m th bits of the numerical value bits of the second calculation result corresponding to the falling edge of the register and is marked as Down 1-Downm.
8. The double edge time-to-digital converter of claim 1, wherein the symbol judging unit comprises 8 buffers BUFF 1-BUFF 8,6 inverters INV 1-INV 6,6 AND gates AND 1-AND 6,2 OR gates OR1, OR2 AND 2D flip-flops DFF1 AND DFF2; BUFF1, BUFF2 and BUFF3 are sequentially connected in series, wherein the input end of BUFF1 is connected with A, the output signals of BUFF1, BUFF2 and BUFF3 are marked as A1, A2 and A3, BUFF4, BUFF5 and BUFF6 are sequentially connected in series, the input end of BUFF4 is connected with B, and the output signals of BUFF4, BUFF5 and BUFF6 are marked as B1, B2 and B3; The input end of the INV1 is connected with the B3, the output end of the INV1 is connected with one input end of the AND1, the other input end of the AND1 is connected with the A3, the output end of the AND1 is connected with the input end of the BUFF7, the output end of the BUFF7 is connected with the data input end of the DFF1, the input end of the INV2 is connected with one input end of the AND2, the other input end of the AND2 is connected with one input end of the OR1, the other input end of the AND3 is connected with the B2, the output end of the AND3 is connected with the other input end of the OR1, the output end of the OR2 is connected with the clock input end of the DFF1, AND the data output end of the DFF1 is used for outputting the sign bit UpSign of the first calculation result corresponding to the rising edges of the A AND the B; The input end of the INV4 is connected with the A3, the output end of the INV4 is connected with one input end of the AND4, the other input end of the AND4 is connected with the B3, the output end of the AND4 is connected with the input end of the BUFF8, the output end of the BUFF8 is connected with the data input end of the DFF2, the input end of the INV5 is connected with one input end of the AND5, the other input end of the AND5 is connected with the A1, the output end of the INV6 is connected with one input end of the AND6, the other input end of the AND6 is connected with the B1, the output end of the AND6 is connected with the other input end of the OR2, the output end of the OR2 is connected with the clock input end of the DFF2, AND the data output end of the DFF2 is used for outputting the sign bit DownSign of the first calculation result represented by the falling edges of the A AND the B.
9. A time domain memory circuit comprises a memory module and is characterized in that the time domain memory circuit adopts the double-edge time digital converter according to any one of claims 1-8, wherein the double-edge time digital converter is used for quantifying a first calculation result of rising edge representation and a second calculation result of falling edge representation of a calculation signal A output by the memory module.
10. A CIM chip, wherein the CIM chip is packaged by the time domain memory circuit as claimed in claim 9.

Description

Double-edge time-to-digital converter, time domain memory circuit and CIM chip Technical Field The invention belongs to the field of integrated circuits, and particularly relates to a double-edge time-to-digital converter, a corresponding time domain memory circuit and a CIM chip. Background In recent years, with the wide application of deep neural networks in the fields of artificial intelligence such as image recognition and natural language processing, the demand for high-energy-efficiency and low-power consumption computing hardware is growing. For an in-memory computing architecture, a time domain method of mapping a computing result into a time difference between a computing signal and a reference signal and converting the time difference into a digital quantity by using a time-to-digital converter is a good solution idea of edge AI application, in a time domain computing circuit, a value of a sign bit of the computing result can be represented by a sequence of rising edges or falling edges of the computing signal and the reference signal, and a value of a numerical bit of the computing result can be represented by a multiplying power of a delay length of the rising edges or the falling edges of the computing signal and the reference signal relative to unit delay. The circuit implementing this quantization function is called a time-to-digital converter (Time to Digital Converter, TDC). On this basis, in order to further improve the computational performance of the circuit, some technicians even design a circuit scheme capable of characterizing both computation results simultaneously by a single computation signal. Wherein a delay difference between the rising edges of the calculated signal and the reference signal is used to characterize the first calculation result and a delay difference between the falling edges of the calculated signal and the reference signal is used to characterize the second calculation result. The circuitry used to quantize such computation results is referred to as a double edge time data converter. Technicians have provided a variety of schemes for double edge time data converters. However, existing dual edge time data converters typically require quantization of rising and falling edges, respectively, by two channels. For example, in Jiahao Song, the paper published by Yuan Wang et al, 2021, 8, the rising and falling edges are processed separately using two channels, the single channel time data converter can only process the rising edge, and to effect processing of the falling edge, the other channel time data converter passes through an inverter to convert the falling edge to the rising edge to effect processing of the falling edge when the calculated waveform is entered. In addition, the time data converter structure of a single channel in the scheme consists of 3D triggers and 1 selector, the structure is simple, and only two unsigned numbers can be quantized, so that the circuit can only process binary data of a BNN network and cannot perform more complex operation. While the dual channel design wastes nearly half the area and power consumption. In addition, in the time-to-digital converter disclosed in the paper published by Chang Xue, youming Yang, equal to month 6 of 2025, one channel represents the time difference of the high bit at the rising edge of quantization, and one channel represents the time difference of the low bit at the falling edge of quantization. In practical application, the time-to-digital converter quantizes the rising edge delay first, and the time data device of the other channel is started to quantize the falling edge delay only if the situation is met, so that the quantization precision and the efficiency scheme are balanced. In addition, the circuit scheme of various double-edge time-to-digital converters with the existing double-channel design mostly adopts a counter to perform time-to-digital conversion, and in order to synchronize time sequence, an external oscillation source is also required, so that new area and power consumption can be introduced, and the circuit performance is further affected. Disclosure of Invention In order to solve the problem that the existing double-edge time data converter adopting the double-channel design is high in common area and power consumption, the invention provides the double-edge time data converter, and a corresponding time domain memory circuit and CIM chip thereof. The invention is realized by adopting the following technical scheme: a double edge time to digital converter for simultaneously effecting quantization of a first computation result representative of a rising edge and a second computation result representative of a falling edge of an input computation signal a within an asynchronous timing. The first calculation result and the second calculation result are signed numbers. The double-edge time-to-digital converter comprises a symbol judging module and a numerical value calculating module.