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CN-122018613-A - LDO circuit

CN122018613ACN 122018613 ACN122018613 ACN 122018613ACN-122018613-A

Abstract

The invention provides an LDO circuit. The LDO circuit comprises a first loop and a second loop, wherein the first loop enables the sampling voltage of the circuit output voltage to be determined by the reference voltage, the first end voltage of the power tube is taken as the circuit output voltage, the second loop can couple the first end voltage of the power tube to the gate end of the power tube through a first capacitor and a first transistor, so that a quick feedback path is formed, the gate end of the power tube can be flexibly changed, and when the output voltage is changed due to transient rapid jump of a load, the gate end voltage of the power tube can be correspondingly and rapidly increased or reduced through the second loop so as to adjust the output current, the response speed of the LDO circuit can be improved, and the work speed of a chip applying the LDO circuit is favorably improved.

Inventors

  • YAN WENRUI

Assignees

  • 兆易创新科技集团股份有限公司

Dates

Publication Date
20260512
Application Date
20241112

Claims (12)

  1. 1. An LDO circuit, comprising: A first loop for sampling the output voltage of the circuit and inputting the obtained sampling voltage and the reference voltage to an operational amplifier, wherein the output voltage of the operational amplifier is coupled with the gate end of a control tube, the first end voltage of the control tube is coupled with the gate end of a power tube after being amplified in multiple stages, the first end voltage of the power tube is taken as the output voltage of the circuit, and And the second loop couples the first end voltage of the power tube to the gate end of the power tube through a first capacitor and a first transistor.
  2. 2. The LDO circuit of claim 1, wherein a first end and a second end of the power tube are coupled to a second end of the control tube and the circuit input voltage, respectively.
  3. 3. The LDO circuit of claim 1, wherein the power tube and the control tube are PMOS tubes, a first terminal voltage of the control tube is a drain terminal voltage of the control tube, and a first terminal voltage of the power tube is a drain terminal voltage of the power tube.
  4. 4. The LDO circuit of claim 1, comprising: The voltage sampling module is used for sampling the circuit output voltage to obtain the sampling voltage, the voltage sampling module comprises a first voltage dividing resistor and a second voltage dividing resistor which are connected in series between the circuit output voltage and the ground, the voltage of a series node of the first voltage dividing resistor and the second voltage dividing resistor is the sampling voltage, and one input end of the operational amplifier is coupled with the sampling voltage while the other input end is coupled with the reference voltage.
  5. 5. The LDO circuit of claim 1, further comprising: And the second capacitor is coupled between the output voltage of the circuit and the input end of the operational amplifier coupled with the sampling voltage.
  6. 6. The LDO circuit of claim 1, comprising a multi-stage amplification structure for multi-stage amplifying the drain voltage of the control tube, the multi-stage amplification structure comprising: a first current mirror unit for mirroring the current flowing through the control tube to a bias current, and And the second current mirror unit is used for mirroring the bias current into the pull-up current of the grid end of the power tube, wherein the pull-down current of the grid end of the power tube is constant.
  7. 7. The LDO circuit of claim 6, wherein the first current mirror unit comprises a second transistor and a third transistor, wherein gate terminals of the second transistor and the third transistor and drain terminals of the second transistor are coupled to the first terminal of the control transistor, source terminals of the second transistor and the third transistor are grounded, the multi-stage amplifying structure further comprises a fourth transistor, source terminals of the fourth transistor are coupled to drain terminals of the third transistor, and gate terminals of the fourth transistor are coupled to an input bias voltage, the input bias voltage enables the fourth transistor to operate in a saturation region.
  8. 8. The LDO circuit of claim 7, wherein the second current mirror unit comprises a fifth transistor and a sixth transistor, gate terminals of the fifth transistor and the sixth transistor and drain terminals of the fifth transistor are coupled to drain terminals of the fourth transistor, source terminals of the fifth transistor and the sixth transistor are coupled to a circuit input voltage, and drain terminals of the sixth transistor are coupled to gate terminals of the power transistor.
  9. 9. The LDO circuit of any of claims 1-8, wherein a gate terminal of the first transistor is coupled to an input bias.
  10. 10. The LDO circuit of any of claims 1-8, wherein a source terminal of the first transistor is coupled to one terminal of the first capacitor, a drain terminal is coupled to a control terminal of the power transistor, and the other terminal of the first capacitor is coupled to the first terminal of the power transistor.
  11. 11. The LDO circuit of any of claims 1-8, further comprising a constant current source coupled between a source of the first transistor and ground, the constant current source to provide a constant pull-down current to the first transistor.
  12. 12. The LDO circuit of any of claims 1-8, further comprising an RC series structure coupled between a circuit input voltage and a control terminal of the power tube.

Description

LDO circuit Technical Field The invention relates to the technical field of circuits, in particular to an LDO circuit. Background With the rapid development of electronic technology, power management chips increasingly play a vital role in various portable electronic devices such as smartphones, tablet computers, or other electronic products. LDO (Low dropout regulator, low dropout linear regulator) is commonly applied to a power management chip due to simple structure and excellent performance so as to realize a voltage stabilizing function. The existing LDO circuit adopts a turnover voltage follower (FVF) to form a FVF-LDO, the grid voltage of a power tube in the circuit is generally lower than the input voltage of the circuit, and when the load current changes, the grid voltage of the power tube cannot change flexibly, so that quick response is difficult to realize. Disclosure of Invention In order to improve the response capability of the LDO when the load current changes, the invention provides an LDO circuit. The LDO circuit provided by the invention comprises: A first loop for sampling the output voltage of the circuit and inputting the obtained sampling voltage and the reference voltage to an operational amplifier, wherein the output voltage of the operational amplifier is coupled with the gate end of a control tube, the first end voltage of the control tube is coupled with the gate end of a power tube after being amplified in multiple stages, the first end voltage of the power tube is taken as the output voltage of the circuit, and And the second loop couples the first end voltage of the power tube to the gate end of the power tube through a first capacitor and a first transistor. Optionally, the first end and the second end of the power tube are coupled to the second end of the control tube and the circuit input voltage, respectively. Optionally, the power tube and the control tube are PMOS tubes, the first end voltage of the control tube is the drain end voltage of the control tube, and the first end voltage of the power tube is the drain end voltage of the power tube. Optionally, the LDO circuit includes: The voltage sampling module is used for sampling the circuit output voltage to obtain the sampling voltage, the voltage sampling module comprises a first voltage dividing resistor and a second voltage dividing resistor which are connected in series between the circuit output voltage and the ground, the voltage of a series node of the first voltage dividing resistor and the second voltage dividing resistor is the sampling voltage, and one input end of the operational amplifier is coupled with the sampling voltage while the other input end is coupled with the reference voltage. Optionally, the LDO circuit further comprises: And the second capacitor is coupled between the output voltage of the circuit and the input end of the operational amplifier coupled with the sampling voltage. Optionally, the LDO circuit includes a multi-stage amplifying structure for amplifying the drain voltage of the control tube in multiple stages, where the multi-stage amplifying structure includes: a first current mirror unit for mirroring the current flowing through the control tube to a bias current, and And the second current mirror unit is used for mirroring the bias current into the pull-up current of the grid end of the power tube, wherein the pull-down current of the grid end of the power tube is constant. Optionally, the first current mirror unit includes a second transistor and a third transistor, gate terminals of the second transistor and the third transistor and drain terminals of the second transistor are coupled to the first terminal of the control transistor, source terminals of the second transistor and the third transistor are grounded, the multistage amplifying structure further includes a fourth transistor, source terminals of the fourth transistor are coupled to the drain terminal of the third transistor, gate terminals of the fourth transistor are coupled to an input bias voltage, and the input bias voltage enables the fourth transistor to operate in a saturation region. Optionally, the second current mirror unit includes a fifth transistor and a sixth transistor, gate terminals of the fifth transistor and the sixth transistor and drain terminals of the fifth transistor are coupled to the drain terminal of the fourth transistor, source terminals of the fifth transistor and the sixth transistor are coupled to the circuit input voltage, and drain terminals of the sixth transistor are coupled to the gate terminal of the power transistor. Optionally, a gate terminal of the first transistor is coupled to an input bias. Optionally, the source end of the first transistor is coupled to one end of the first capacitor, the drain end is coupled to the control end of the power tube, and the other end of the first capacitor is coupled to the first end of the power tube. Optionally, the LDO circuit further includ