CN-122018615-A - Reference current generator for nonvolatile memory

CN122018615ACN 122018615 ACN122018615 ACN 122018615ACN-122018615-A

Abstract

A reference current generator includes two transistors, a resistor and a mirror circuit. The source of the first transistor receives the power supply voltage, the drain is connected to the first node, and the gate is connected to the second node. The source electrode of the second transistor receives the power supply voltage, and the drain electrode and the grid electrode of the second transistor are connected to the third node. The resistor is connected between the second node and the third node. The input end of the mirror circuit receives an input current, the first mirror end is connected to the second node, and the second mirror end is connected to the first node. The first mirror end and the second mirror end respectively generate a first mirror current and a second mirror current. Wherein the first transistor generates a saturation current. In addition, the reference current is equal to the saturation current minus the second mirror current.

Inventors

ZHANG ZHEWEI
GU WEIMING

Assignees

力旺电子股份有限公司

Dates

Publication Date: 20260512
Application Date: 20251107
Priority Date: 20241112

Claims (13)

1. A reference current generator for use in a non-volatile memory, the reference current generator comprising: a first transistor, a source of the first transistor receiving a first power voltage, a drain of the first transistor being connected to a first node, a gate of the first transistor being connected to a second node; A second transistor, a source of the second transistor receives the first power voltage, a drain of the second transistor is connected to a third node, and a gate of the second transistor is connected to the third node; a first resistor having a first end connected to the third node and a second end connected to the second node, and The first mirror circuit comprises a first node, a second node, a first mirror circuit, a second mirror circuit, a first voltage regulator and a second voltage regulator, wherein an input end of the first mirror circuit receives an input current, a first mirror end of the first mirror circuit is connected to the second node, a second mirror end of the first mirror circuit is connected to the first node, a first mirror current is generated by the first mirror end of the first mirror circuit, a second mirror current is generated by the second mirror end of the first mirror circuit, and a first proportional relation exists among the input current, the first mirror current and the second mirror current; the first transistor and the second transistor operate in a saturation mode, and the first transistor generates a saturation current; The reference current generator outputs a first reference current, and the first reference current is equal to the saturation current minus the second mirror current.
2. The reference current generator of claim 1, wherein the first resistor has a voltage drop, an overdrive voltage of the first transistor is at least five times greater than the voltage drop, and the overdrive voltage is equal to a source gate voltage of the first transistor plus a threshold voltage of the first transistor.
3. The reference current generator of claim 1, wherein the first mirror circuit comprises: A third transistor, a drain of which receives the input current, a gate of which is connected to the drain of the third transistor, a source of which receives a second power supply voltage; A fourth transistor having a drain connected to the second node, a gate connected to the gate of the third transistor, a source receiving the second power supply voltage, and A fifth transistor having a drain connected to the first node, a gate connected to the gate of the third transistor, and a source receiving the second power supply voltage; wherein the first power supply voltage is greater than the second power supply voltage.
4. The reference current generator of claim 1, further comprising a current source that generates the input current and inputs the input of the first mirror circuit.
5. The reference current generator of claim 1, further comprising: a band gap reference circuit, which generates a band gap voltage; A second resistor, a first end of which is connected to a fourth node, and a second end of which receives a second supply voltage; a second mirror circuit having an input terminal connected to the fourth node for receiving a first current, an image terminal generating the input current, and An inverting input terminal of the operational amplifier receives the bandgap voltage, a non-inverting input terminal of the operational amplifier is connected to the fourth node, and an output terminal of the operational amplifier is connected to the second mirror circuit for controlling the second mirror circuit.
6. The reference current generator of claim 5, wherein the first current is equal to the bandgap voltage divided by the resistance of the second resistor, and there is a second proportional relationship between the first current and the input current.
7. The reference current generator of claim 5, wherein the first resistor and the second resistor are polysilicon resistors.
8. The reference current generator of claim 5, wherein the second mirror circuit comprises: a third transistor having a source receiving the first supply voltage, a gate connected to the output terminal of the operational amplifier, a drain connected to the fourth node, and A source of the fourth transistor receives the first supply voltage, a gate of the fourth transistor is connected to the output end of the operational amplifier, and a drain of the fourth transistor generates the input current; wherein the first power supply voltage is greater than the second power supply voltage.
9. The reference current generator of claim 1, further comprising a second mirror circuit having an input coupled to the first node for receiving the first reference current, a mirror of the second mirror circuit outputting a second reference current, the first reference current and the second reference current having a second proportional relationship.
10. The reference current generator of claim 9, wherein the second mirror circuit comprises: A third transistor having a drain connected to the first node for receiving the first reference current, a gate connected to the drain of the third transistor, a source receiving a second power supply voltage, and A fourth transistor, a drain electrode of the fourth transistor is the mirror end of the second mirror circuit to generate the second reference current, a gate electrode of the fourth transistor is connected to the gate electrode of the third transistor, and a source electrode of the fourth transistor receives the second power supply voltage; wherein the first power supply voltage is greater than the second power supply voltage.
11. The reference current generator of claim 9, wherein the second mirror circuit comprises: a third transistor having a drain connected to the first node for receiving the first reference current, a gate connected to the drain of the third transistor, and a source for receiving a second supply voltage; a gate of the fourth transistor is connected to the gate of the third transistor, and a source of the fourth transistor receives the second power supply voltage; A fifth transistor, a drain of which is connected to a drain of the fourth transistor, a gate of which is connected to the drain of the fifth transistor, a source of which receives the first power voltage; a sixth transistor, a drain electrode of the sixth transistor is the mirror end of the second mirror circuit to generate the second reference current, a gate electrode of the sixth transistor is connected to the gate electrode of the fifth transistor, and a source electrode of the sixth transistor receives the first power supply voltage; wherein the first power supply voltage is greater than the second power supply voltage.
12. The reference current generator of claim 9, wherein the nonvolatile memory comprises a memory cell and a sensing circuit, wherein the sensing circuit receives a memory cell current and the second reference current generated by the memory cell during a read operation, and determines a storage state of the memory cell according to the memory cell current and the second reference current.
13. The reference current generator of claim 12, wherein the memory cell is in a programmed state when the memory cell current is greater than the second reference current, and wherein the memory cell is in an erased state when the memory cell current is less than the second reference current.

Description

Reference current generator for nonvolatile memory Technical Field The present invention relates to a current generator, and more particularly to a reference current generator for a nonvolatile memory. Prior Art As is well known, a nonvolatile memory includes a memory cell array (memory CELL ARRAY) that is formed of a plurality of memory cells, and the memory cells are nonvolatile memory cells. Furthermore, each nonvolatile memory unit comprises a storage unit. For example, the storage cell is a floating gate transistor (floating gate transistor). The storage state of the nonvolatile memory cell can be determined according to the number of carriers (carriers) stored in the floating gate transistor. For example, the floating gate transistor is a P-type floating gate transistor and the carrier is electrons. During programming of the memory cell, the floating gate of the electron injection (object) floating gate transistor may be controlled to represent a floating gate storage carrier. At this time, the memory cell is in a programmed state (on state) or called an programmed state (programmed state). During an erase operation of the memory cell, the floating gate of the electron exit (e-ject) floating gate transistor may be controlled to indicate that the floating gate is not storing carriers. At this time, the memory cell is in an erased state (ERASED STATE), or referred to as an off state (off state). Wherein the on state and the off state represent two different storage states of the memory cell. Of course, the memory cells of the memory cells may also be N-type floating gate transistors. Controlling the number of floating gate carriers stored in the floating gate transistor can also cause the memory cell to be turned on or off. Furthermore, when a memory cell is read, the memory cell in the on state may generate a larger memory cell current (cell current), or referred to as an on current (on current). The off-state memory cell may produce a smaller memory cell current, or referred to as an off current (off current). That is, during the reading operation, the storage state of the memory cell can be determined according to the magnitude of the memory cell current generated by the memory cell. To determine the storage state of the memory cell, a reference current generator (REFERENCE CURRENT GENERATOR) and a sensing circuit (sensing circuit) are designed in the nonvolatile memory. The reference current generator generates a reference current, and the reference current is set between an on current and an off current. During the reading operation, the sensing circuit receives the reference current and the memory cell current generated by the memory cell, and determines the storage state of the memory cell. When the memory cell current is greater than the reference current, the sensing circuit determines whether the memory cell is in a programmed state or an on state. When the memory cell current is smaller than the reference current, the sensing circuit judges that the memory cell is in an erasing state or an off state. Basically, when the nonvolatile memory is manufactured and tested, it is possible to confirm which manufacturing process corner the nonvolatile memory belongs to. Furthermore, memory cell current levels of memory cells are affected by different process corners (process corners) and operating temperatures. Referring to fig. 1, a schematic diagram of memory cell current and reference current for various manufacturing process corners and operating temperatures in a conventional nonvolatile memory is shown. All memory cells of the typical-typical corner (TT corner) are read and counted. At an operating temperature of-40 ℃, the minimum on current (min I ON) is about 18 μa among the on-state memory cells. Among the memory cells in the off state, the maximum off current (max. I OFF) is about 1 μa. At an operating temperature of 25 ℃, the minimum on current in the on-state memory cell is about 16 μa. The maximum off current in the off state memory cell is about 1 mua. At an operating temperature of 150 ℃, the minimum on current in the on-state memory cell is about 14 μa. The maximum off current in the off state memory cell is about 2 mua. All memory cells of the fast-fast corner (FF corner) are read and counted. At an operating temperature of-40 ℃, the minimum on-current in the on-state memory cell is about 20 μa. The maximum off current in the off state memory cell is about 1 mua. At an operating temperature of 25 ℃, the minimum on current in the on-state memory cell is about 18 μa. The maximum off current in the off state memory cell is about 2 mua. At an operating temperature of 150 ℃, the minimum on current in the on-state memory cell is about 14 μa. The maximum off current in the off state memory cell is about 3 mua. And all storage units of slow-slow corner (SS corner) are read and counted. At an operating temperature of-40 ℃, the minimum on-current in the on-state memory cell is about 16 μa. The m