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CN-122018616-A - Chip with current mirror type voltage source

CN122018616ACN 122018616 ACN122018616 ACN 122018616ACN-122018616-A

Abstract

A chip having a current mirror type voltage source including a first n-channel metal oxide semiconductor field effect transistor (NMOS) and a second NMOS whose drains are coupled to a first voltage source, and an operational amplifier whose outputs are coupled to gates of the first NMOS and the second NMOS, whose negative inputs are coupled to sources of the first NMOS to form a negative feedback loop, and whose positive inputs are coupled to sources of the second NMOS to form a positive feedback loop, wherein the operational amplifier is powered by a second voltage source larger than the first voltage source such that the first NMOS and the second NMOS operate in a saturation region, thereby causing the current mirror type voltage source to output a load current mirrored with a first current. In this way, the gates of the first and second NMOS are controlled by the output of the operational amplifier, which is more tolerant to the pair of NMOS operating voltage margins.

Inventors

  • HUANG JINGHAO

Assignees

  • 联发科技股份有限公司

Dates

Publication Date
20260512
Application Date
20251112
Priority Date
20241112

Claims (11)

  1. 1. A chip having a current mirror voltage source, the current mirror voltage source comprising: A first n-channel metal oxide semiconductor field effect transistor (NMOS) and a second NMOS having their drains coupled to a first voltage source, and An operational amplifier, the output end of which is coupled to the grid electrodes of the first NMOS and the second NMOS, the negative input end of which is coupled to the source electrode of the first NMOS to form a negative feedback loop, and the positive input end of which is coupled to the source electrode of the second NMOS to form a positive feedback loop; the operational amplifier is powered by a second voltage source larger than the first voltage source, so that the first NMOS and the second NMOS work in a saturation region, and the current mirror type voltage source outputs load current mirrored with the first current.
  2. 2. The chip of claim 1, further comprising: and a low-resistance load driven by the load current, wherein the resistance of the low-resistance load is lower than a threshold value, and the threshold value ensures that the current mirror type voltage source works in a stable region.
  3. 3. The chip of claim 2, wherein the chip, The threshold depends on the first resistance and the size ratio of the second NMOS to the first NMOS; the first resistor is determined by V1/I1, wherein I1 is a first current, V1 is a voltage at a first connection node between the negative input terminal of the operational amplifier and the first NMOS source, and The low-resistance load is coupled to a second connection node between the positive input terminal of the operational amplifier and the second NMOS source.
  4. 4. The chip of claim 3, wherein the chip, The threshold value is R1/M, Wherein R1 is a first resistor, and M is the size ratio of the second NMOS to the first NMOS.
  5. 5. The chip of claim 1, further comprising: a charge pump pumping the first voltage source to a second voltage source, and And a low-pass filter at the output of the charge pump for filtering the second voltage source and coupling the filtered second voltage source to the operational amplifier.
  6. 6. The chip of claim 1, wherein the chip comprises a plurality of chips, The first voltage source and the second voltage source are external voltage sources coupled to the chip.
  7. 7. The chip of claim 1, wherein the chip comprises a plurality of chips, A first connection node between the negative input end of the operational amplifier and the first NMOS source electrode is at a first voltage V1; A second connection node between the positive input end of the operational amplifier and the second NMOS source electrode is at a second voltage V2; The operational amplifier outputs a third voltage V3; v3 is greater than V1 plus Vth1, where Vth1 is the threshold voltage of the first NMOS, and V3 is greater than V2 plus Vth2, where Vth2 is the threshold voltage of the second NMOS.
  8. 8. The chip of claim 7, wherein the chip, V3 is less than Vdd1 plus Vth1, and also less than Vdd1 plus Vth2, where Vdd1 is the first voltage source.
  9. 9. The chip of claim 1, wherein the chip comprises a plurality of chips, The drains of the first and second NMOS are directly coupled to the first voltage source without passing through any transistor, or/and the source of the second NMOS is directly coupled to a low-resistance load driven by the load current without passing through any transistor.
  10. 10. The chip of claim 1, further comprising: A current mirror coupled to a first connection node between the negative input of the operational amplifier and the source of the first NMOS for determining the first current.
  11. 11. The chip of claim 3, further comprising: And a third NMOS having a drain coupled to the second connection node to provide an additional current path to regulate the load current driving the low-resistance load.

Description

Chip with current mirror type voltage source Technical Field The invention relates to the technical field of chips, in particular to a chip with a current mirror type voltage source. Background Fig. 1 illustrates a conventional chip power supply design. As shown, a low dropout linear regulator (low-dropout regulator, LDO) 102 and a current mirror 104 are used to power a load RL. LDO 102 employs n-channel metal Oxide semiconductor field effect transistor (NMOS) Mn as a power MOS to increase a Power Supply Rejection Ratio (PSRR). The regulated voltage (e.g., 0.85V) generated by LDO 102 powers current mirror 104, and current mirror 104 generates load current IL to drive load RL. The current mirror 104 employs a p-channel metal Oxide semiconductor field effect transistor (p-CHANNEL METAL-Oxide-Semiconductor Field-Effect Transistor, PMOS) Mp to provide a load current IL to the load RL. The cascaded (cascaded) NMOS Mn and PMOS MP need to share a limited dynamic margin (e.g., 1V-0.6V). PMOS Mp may introduce a supply jitter (power supply jitter, PSJ) from the 1V voltage source to the load RL, which typically may be 3% -5% UI (UI is an abbreviation of Unit Interval (UI) in high-speed SerDes applications). Disclosure of Invention In view of this, the present invention provides a novel chip with a novel power supply design that includes a voltage supply structure that operates as a current source with an improved power supply rejection ratio (power supply rejection ratio, PSRR). This voltage source structure is also called current-mirror-like voltage source. In one exemplary embodiment, a chip with a current mirror type voltage source is shown. The current mirror voltage source includes a first n-channel metal oxide semiconductor field effect transistor (NMOS), a second NMOS, and an operational amplifier. The drains of the first NMOS and the second NMOS are coupled to a first voltage source. The output end of the operational amplifier is coupled to the gates of the first NMOS and the second NMOS, the negative input end of the operational amplifier is coupled to the source electrode of the first NMOS to form a negative feedback loop, and the positive input end of the operational amplifier is coupled to the source electrode of the second NMOS to form a positive feedback loop. The operational amplifier is powered by a second voltage source that is larger than the first voltage source to operate the first NMOS and the second NMO in a saturation region to cause the current mirror voltage source to output a load current that mirrors the first current. In one exemplary embodiment, the chip also has a low resistive load. The low-resistance load is driven by a load current, and the resistance of the low-resistance load is lower than a threshold value, so that the current mirror type voltage source is ensured to work in a stable region of the low-resistance load. In one exemplary embodiment, the chip also has a charge pump and a low pass filter. The charge pump pumps current from a first voltage source to a second voltage source. The low pass filter is coupled to the output of the charge pump for filtering the second voltage source and coupling the filtered second voltage source to the operational amplifier. In this way, power Supply Jitter (PSJ) introduced to the load is significantly suppressed. In an exemplary embodiment, the drains of the first and second NMOS are directly coupled to the first voltage source without passing through any transistor. In one exemplary embodiment, the source of the second NMOS is directly coupled to the low-resistance load without passing through any transistor. Thereby providing a stable current to the load RL. Further, the current mirror voltage source further comprises a low-resistance load driven by the load current, wherein the resistance of the low-resistance load is lower than a threshold value, and the threshold value ensures that the current mirror voltage source works in a stable area. Further, the threshold depends on a first resistance, and a size ratio of the second NMOS to the first NMOS, the first resistance is determined by V1/I1, where I1 is a first current, V1 is a voltage at a first connection node between a negative input of the operational amplifier and a first NMOS source, and the low resistance load is coupled to a second connection node between a positive input of the operational amplifier and the second NMOS source. Further, the threshold is R1/M, wherein R1 is a first resistor and M is a size ratio of the second NMOS to the first NMOS. Further, a ring oscillator driven by the load current is included. Thereby driving the ring oscillator to operate stably. Further, the charge pump is used for pumping the first voltage source to the second voltage source, and the low-pass filter is positioned at the output end of the charge pump and used for filtering the second voltage source and coupling the filtered second voltage source to the operational amplifier. Thus, a stable and