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CN-122018620-A - Linear voltage stabilizer

CN122018620ACN 122018620 ACN122018620 ACN 122018620ACN-122018620-A

Abstract

The invention discloses a linear voltage stabilizer, which relates to the technical field of electronic circuits, wherein an overshoot suppression circuit is arranged at a voltage output end of the linear voltage stabilizer, the first regulating circuit is used for regulating the grid voltage of a first transistor based on the grid voltage of a second transistor when the voltage output end is not overshot, the grid source voltage of the first transistor is triggered to be rapidly increased along with the voltage change of the voltage output end during overshoot to form a current leakage path to the ground, an undershoot suppression circuit is arranged at the grid electrode of a power tube of the linear voltage stabilizer, the second regulating circuit is used for maintaining the static working state of a third transistor when the voltage output end is not undershot, the grid voltage of the third transistor is triggered to be changed along with the voltage output end during undershoot to enable the third transistor to trigger the power tube to rapidly supplement current to a load capacitor, the undershoot state of the voltage output end is suppressed, and the overshoot and undershoot problems of the voltage output end of the linear voltage stabilizer can be suppressed, and the undershoot circuit is well influenced by environmental changes such as process and temperature.

Inventors

  • Yuan Chenchong

Assignees

  • 无锡有容微电子有限公司

Dates

Publication Date
20260512
Application Date
20260317

Claims (10)

  1. 1. A linear voltage stabilizer is characterized by comprising an error amplifier, a power tube, a feedback circuit, an overshoot suppression circuit and an undershoot suppression circuit; The overshoot suppression circuit comprises a first transistor, a second transistor, a first current source and a first regulating circuit, wherein the first transistor is arranged between a voltage output end of the linear voltage stabilizer and ground, the second transistor is connected in series with the first current source and is connected between a direct current power supply and the ground, a grid electrode of the second transistor is connected with a drain electrode, the first regulating circuit is arranged between the grid electrode of the first transistor and the grid electrode of the second transistor, and the first regulating circuit is used for regulating the grid electrode voltage of the first transistor based on the grid electrode voltage of the second transistor when the voltage output end is not in an overshoot state, and triggering the grid electrode voltage of the first transistor to change along with the voltage output end to form a current leakage path from the voltage output end to the ground end when the voltage output end is in an overshoot state; The undershoot suppression circuit comprises a third transistor and a second regulating circuit, wherein the third transistor is arranged between the grid electrode of the power tube and the ground, the first end of the second regulating circuit is connected with the voltage output end, the second end of the second regulating circuit is connected with the grid electrode of the third transistor, the third transistor is used for maintaining the static working state of the third transistor when the voltage output end is not in an undershoot state, and when the voltage output end is in an undershoot state, the grid electrode voltage of the third transistor is triggered to change along with the voltage output end so that the third transistor triggers the power tube to suppress the undershoot state of the voltage output end.
  2. 2. The linear regulator of claim 1, wherein the first regulation circuit comprises a common source amplifier and an operational amplifier; the signal input end of the common source amplifier is connected with the voltage output end, the signal output end of the common source amplifier is connected with the grid electrode of the first transistor, the grid electrode of the amplifying tube in the common source amplifier is connected with the output end of the operational amplifier, and the two input ends of the operational amplifier are respectively connected with the grid electrode of the first transistor and the grid electrode of the second transistor.
  3. 3. The linear voltage regulator of claim 2, wherein the first transistor and the second transistor are NMOS transistors.
  4. 4. The linear voltage regulator of claim 2, wherein the common source amplifier comprises a fourth transistor and a fifth transistor; The source of the fourth transistor is the signal input end of the common source amplifier, the drain electrode of the fourth transistor is connected with the drain electrode of the fifth transistor, the grid electrode of the fourth transistor is connected with the output end of the operational amplifier, the source electrode of the fifth transistor is grounded, and the grid electrode of the fifth transistor is connected with the grid electrode of the second transistor.
  5. 5. The linear voltage regulator of claim 2, wherein the first regulation circuit further comprises a first capacitor disposed between the dc power supply and the output of the operational amplifier.
  6. 6. The linear regulator of claim 1, wherein the second regulation circuit comprises a second capacitor and a first voltage clamp circuit; The second capacitor is arranged between the grid electrode of the third transistor and the ground, the output end of the first voltage clamping circuit is connected with the grid electrode of the third transistor, and the first voltage clamping circuit is used for maintaining the static working state of the third transistor when the voltage output end is not in an undershoot state.
  7. 7. The linear voltage regulator of claim 2, wherein the first voltage clamp circuit comprises a second current source, a sixth transistor, a seventh transistor, and an eighth transistor; the third transistor and the eighth transistor are PMOS transistors, and the sixth transistor and the seventh transistor are NMOS transistors; The first end of the second current source is connected with a direct current power supply, the second end of the second current source is connected with the drain electrode of the sixth transistor, the grid electrode of the sixth transistor and the grid electrode of the seventh transistor, the source electrode of the sixth transistor and the source electrode of the seventh transistor are grounded, the drain electrode of the seventh transistor, the drain electrode of the eighth transistor, the grid electrode of the eighth transistor and the grid electrode of the third transistor are connected with the first end of the second capacitor, the source electrode of the eighth transistor and the source electrode of the third transistor are connected with the grid electrode of the power transistor, the drain electrode of the third transistor is grounded, and the second end of the second capacitor is connected with the voltage output end.
  8. 8. The linear voltage regulator of claim 1, further comprising a source follower disposed between the output of the error amplifier and the gate of the power tube.
  9. 9. The linear voltage regulator of claim 1, wherein the feedback circuit comprises a first resistor and a second resistor connected in series and connected between the voltage output and ground, a junction of the first resistor and the second resistor being connected to the positive input of the error amplifier.
  10. 10. The linear voltage regulator according to any one of claims 1 to 9, wherein the source follower of the error amplifier, the undershoot suppression circuit, and the power transistor are configured as N driving units connected in parallel, and each of the driving units includes one of the source follower, the undershoot suppression circuit, and the power transistor.

Description

Linear voltage stabilizer Technical Field The invention relates to the technical field of electronic circuits, in particular to a linear voltage stabilizer. Background Low dropout linear regulators (Low Dropout Regulator, LDOs) are widely used in power management integrated circuits due to their low noise, high accuracy and simple structure. In order to maintain loop stability and suppress output voltage fluctuation, a load capacitor with larger capacity is usually connected to the outside of the chip in the conventional LDO. The off-chip capacitor occupies a larger Printed Circuit Board (PCB) area, increases system cost and volume, and is unfavorable for high integration and miniaturization development of electronic devices. To overcome this drawback, design of an off-chip capacitor (Capless) LDO has been developed. The LDO removes huge off-chip capacitance, and a relatively small load capacitance is integrated in a chip, so that when the load current of the LDO is subjected to rapid and large-amplitude step change, the LDO cannot timely adjust a power tube to respond to the current demand of the load, and further larger overshoot or undershoot voltage is generated at the voltage output end of the LDO, the recovery time is longer, and the stable work and the performance of the load are influenced. Therefore, how to suppress the overshoot voltage or undershoot voltage generated by the linear voltage regulator without off-chip capacitor when the load current suddenly changes is a technical problem that needs to be solved by those skilled in the art. Disclosure of Invention The invention provides a linear voltage stabilizer, which at least solves the problem that the linear voltage stabilizer without an off-chip capacitor in the related art generates overshoot voltage or undershoot voltage when load current suddenly changes. In order to solve the technical problems, the invention provides a linear voltage stabilizer, which comprises an error amplifier, a power tube, a feedback circuit, an overshoot suppression circuit and an undershoot suppression circuit; The overshoot suppression circuit comprises a first transistor, a second transistor, a first current source and a first regulating circuit, wherein the first transistor is arranged between a voltage output end of the linear voltage stabilizer and ground, the second transistor is connected in series with the first current source and is connected between a direct current power supply and the ground, a grid electrode of the second transistor is connected with a drain electrode, the first regulating circuit is arranged between the grid electrode of the first transistor and the grid electrode of the second transistor, and the first regulating circuit is used for regulating the grid electrode voltage of the first transistor based on the grid electrode voltage of the second transistor when the voltage output end is not in an overshoot state, and triggering the grid electrode voltage of the first transistor to change along with the voltage output end to form a current leakage path from the voltage output end to the ground end when the voltage output end is in an overshoot state; The undershoot suppression circuit comprises a third transistor and a second regulating circuit, wherein the third transistor is arranged between the grid electrode of the power tube and the ground, the first end of the second regulating circuit is connected with the voltage output end, the second end of the second regulating circuit is connected with the grid electrode of the third transistor, the third transistor is used for maintaining the static working state of the third transistor when the voltage output end is not in an undershoot state, and when the voltage output end is in an undershoot state, the grid electrode voltage of the third transistor is triggered to change along with the voltage output end so that the third transistor triggers the power tube to suppress the undershoot state of the voltage output end. Optionally, the first adjusting circuit includes a common source amplifier and an operational amplifier; the signal input end of the common source amplifier is connected with the voltage output end, the signal output end of the common source amplifier is connected with the grid electrode of the first transistor, the grid electrode of the amplifying tube in the common source amplifier is connected with the output end of the operational amplifier, and the two input ends of the operational amplifier are respectively connected with the grid electrode of the first transistor and the grid electrode of the second transistor. Optionally, the first transistor and the second transistor are both NMOS transistors. Optionally, the common source amplifier includes a fourth transistor and a fifth transistor; The source of the fourth transistor is the signal input end of the common source amplifier, the drain electrode of the fourth transistor is connected with the drain electrode of the fif