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CN-122018621-A - LDO circuit with high power supply rejection ratio

CN122018621ACN 122018621 ACN122018621 ACN 122018621ACN-122018621-A

Abstract

The invention provides an LDO circuit with a high power supply rejection ratio, and belongs to the technical field of power supply management. The invention uses a series multistage buffer structure which is provided with multistage series buffers and segmented power tubes, wherein the series buffers gradually drive the segmented power tubes, can effectively transfer non-main pole points in a circuit to higher frequency and introduce beneficial feedforward zero points to perform zero pole cancellation, so that the advantage of better PSR in a wide frequency range of an LDO with an output pole as the main pole point can be fully utilized while a smaller on-chip capacitor is used, the LDO based on an FVF structure is used, and the gain of a direct current loop is compensated by adding a slow loop to an error amplification module, so that the feedback loop of the LDO has enough phase margin while the fast alternating current loop response is provided, the SRC structure with ripple injection is selected, and the PSR performance of the LDO under high frequency can be further enhanced by designing the high PSR of the buffer.

Inventors

  • ZHONG HUI
  • LV KELIN

Assignees

  • 电子科技大学

Dates

Publication Date
20260512
Application Date
20260324

Claims (8)

  1. 1. The LDO circuit with the high power supply rejection ratio is characterized by comprising a reference module REF, an error amplifier module EA, a first buffer B1, a second buffer B2, a third buffer B3, a fourth buffer B4, a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6, a seventh MOS tube M7, a first power tube M P1 , a second power tube M P2 , a third power tube M P3 , a fourth power tube M P4 , a first resistor R 1 , a second resistor R 2 , a third resistor R F , a first capacitor C C , a second capacitor C F , a third capacitor C L , a first current source I B1 and a second current source I B2 ; The drain electrode of the first MOS tube M1 is connected with the grid electrode of the second MOS tube M2 and the input end of the first current source I B1 , the grid electrode of the first MOS tube M1 is connected with the output end of the error amplifier module EA, the grid electrode of the sixth MOS tube M6 and one end of the first capacitor C C , and the source electrode of the first MOS tube M1 is connected with the output end V OUT of the LDO circuit, the drain electrode of the first power tube M P1 , the drain electrode of the second power tube M P2 , the drain electrode of the third power tube M P3 , the drain electrode of the fourth power tube M P4 , One end of the first resistor R 1 and one end of the third capacitor C L , the drain electrode of the second MOS tube M2 is grounded, the source electrode of the second MOS tube M2 is connected with the drain electrode of the fourth MOS tube M4, the grid electrode of the fifth MOS tube M5 and the input end of the first buffer B1, the drain electrode of the third MOS tube M3 is connected with the grid electrode of the third MOS tube, one end of the third resistor R F , the input end of the second current source I B2 , the source electrode of the third MOS tube M3 is connected with a power supply, the grid electrode of the fourth MOS tube M4 is connected with the other end of the third resistor R F and one end of the second capacitor C F , the source electrode of the fourth MOS tube M4 is connected with the power supply, the drain electrode of the fifth MOS tube M5 is connected with the source electrode of the sixth MOS tube M6, the source electrode of the fifth MOS tube M5 is connected with the power supply, the drain electrode of the sixth MOS tube M6 is connected with the drain electrode and the grid electrode of the seventh MOS tube M7, the first buffer B1, The load current self-adaptive bias structure input ends of the second buffer B2, the third buffer B3 and the fourth buffer B4, the source electrode of the seventh MOS tube M7 is grounded, the grid electrode of the first power tube M P1 is connected with the output end of the first buffer B1 and the input end of the second buffer B2, the source electrode of the first power tube M P1 is connected with a power supply, the grid electrode of the second power tube M P2 is connected with the output end of the second buffer B2, The input end of the third buffer B3, the source electrode of the second power tube M P2 is connected with a power supply, the grid electrode of the third power tube M P3 is connected with the output end of the third buffer B3, The input end of the fourth buffer B4, the source electrode of the third power tube M P3 is connected with a power supply, the grid electrode of the fourth power tube M P1 is connected with the output end of the fourth buffer B4, the source electrode of the fourth power tube M P1 is connected with the power supply, the other end of the first resistor R 1 is connected with the negative input end of the error amplifier module EA, One end of the second resistor R 2 , the other end of the second resistor R 2 is grounded, the other end of the first capacitor C C is grounded, the other end of the second capacitor C F is grounded, the other end of the third capacitor C L is grounded, the output end of the reference module REF is connected with the positive input end of the error amplifier module EA, the output end of the first current source I B1 is grounded, the output end of the second current source I B2 is grounded.
  2. 2. The LDO circuit of claim 1, wherein the reference module REF is configured to generate a reference voltage output to the error amplifier module EA, and wherein the error amplifier module EA is configured to use a folded cascode amplifier.
  3. 3. The LDO circuit with high power supply rejection ratio as claimed in claim 1, wherein the fifth MOS transistor M5, the sixth MOS transistor M6 and the seventh MOS transistor M7 form a load current self-adaptive bias structure, the load current is copied in proportion and transferred into each stage of buffer, the first MOS transistor M1 and the second MOS transistor M2 form a fast loop together with each stage of buffer and each stage of power transistor, and the first MOS transistor M1 forms a slow loop together with the first resistor R 1 , the second resistor R 2 and the error amplifier.
  4. 4. The LDO circuit of claim 1, wherein the third MOS transistor M3, the fourth MOS transistor M4, the third resistor R F , and the second capacitor C F form a ripple injection SRC structure.
  5. 5. The LDO circuit with high power supply rejection ratio according to claim 1, wherein the first buffer B1, the second buffer B2, the third buffer B3 and the fourth buffer B4 form a series multistage buffer structure, the circuit structures of the first buffer B1, the second buffer B2, the third buffer B3 and the fourth buffer B4 are identical, and each buffer comprises a first MOS tube M B1 , a second MOS tube M B2 , a third MOS tube M B3 , a fourth MOS tube M B4 , a fifth MOS tube M B5 , a sixth MOS tube M B6 , a seventh MOS tube M B7 , an eighth MOS tube M B8 , a ninth MOS tube M B9 , a tenth MOS tube M B10 , an eleventh MOS tube M B11 , a twelfth MOS tube M B12 , a thirteenth MOS tube M B13 and a current source I B3 .
  6. 6. The LDO circuit with high power supply rejection ratio as claimed in claim 5, wherein the drain of the first MOS transistor M B1 is connected with the drain and gate of the fourth MOS transistor M B4 , the gate of the sixth MOS transistor M B6 , The drain electrode of the thirteenth MOS tube M B13 , the grid electrode of the first MOS tube M B1 is connected with the input end of the buffer, the source electrode of the first MOS tube M B1 is connected with the source electrode of the second MOS tube M B2 , The drain electrode of the tenth MOS tube M B10 and the input end of the current source I B3 , the drain electrode of the second MOS tube M B2 is connected with the drain electrode and the grid electrode of the third MOS tube M B3 , The grid electrode of the fifth MOS tube M B5 , the drain electrode of the twelfth MOS tube M B12 , the grid electrode of the second MOS tube M B2 connected with the output end of the buffer, the drain electrode of the sixth MOS tube M B6 , The drain electrode of the eighth MOS tube M B8 , the source electrode of the third MOS tube M B3 is connected with a power supply, the source electrode of the fourth MOS tube M B4 is connected with a power supply, the drain electrode of the fifth MOS tube M B5 is connected with the drain electrode and the grid electrode of the seventh MOS tube M B7 , The grid electrode of the eighth MOS tube M B8 , the source electrode of the fifth MOS tube M B5 is connected with a power supply, the source electrode of the sixth MOS tube M B6 is connected with a power supply, the source electrode of the seventh MOS tube M B7 is grounded, the source electrode of the eighth MOS tube M B8 is grounded, the drain electrode of the ninth MOS tube M B9 is connected with the drain electrode and the grid electrode of the eleventh MOS tube M B11 , The grid electrode of the twelfth MOS tube M B12 , the grid electrode of the thirteenth MOS tube M B13 , the grid electrode of the ninth MOS tube M B9 connected with the input end of the load current self-adaptive bias structure, The grid electrode of the tenth MOS tube M B10 , the source electrode of the ninth MOS tube M B9 are grounded, the source electrode of the tenth MOS tube M B10 is grounded, the source electrode of the eleventh MOS tube M B11 is connected with a power supply, the source electrode of the twelfth MOS tube M B12 is connected with a power supply, the source electrode of the thirteenth MOS tube M B13 is connected with a power supply, and the output end of the current source I B3 is grounded.
  7. 7. The LDO circuit with high power supply rejection ratio according to claim 6, wherein the ninth MOS transistor M B9 , the tenth MOS transistor M B10 , the eleventh MOS transistor M B11 , the twelfth MOS transistor M B12 and the thirteenth MOS transistor M B13 form a component part of the load current self-adaptive bias structure positioned in the buffer, and the first MOS transistor M B1 , the second MOS transistor M B2 , the third MOS transistor M B3 , the fourth MOS transistor M B4 , the fifth MOS transistor M B5 , the sixth MOS transistor M B6 , the seventh MOS transistor M B7 and the eighth MOS transistor M B8 form a main body structure of the buffer.
  8. 8. The LDO circuit of claim 7, wherein the power supply ripple is transferred to the buffer output through two transfer paths, one transfer path from the power supply through the fifth MOS transistor M B5 , the seventh MOS transistor M B7 , the eighth MOS transistor M B8 to the buffer output, and the other transfer path from the power supply through the sixth MOS transistor M B6 to the buffer output.

Description

LDO circuit with high power supply rejection ratio Technical Field The invention belongs to the technical field of power management, and particularly relates to an LDO circuit with a high power supply rejection ratio. Background In various voltage stabilizing circuits, the LDO (Low Dropout Regulator, low dropout linear voltage regulator) has small output voltage ripple and strong power supply interference suppression capability, and the LDO has good energy conversion efficiency due to low enough voltage difference. An off-chip capacitor LDO with an Internal Pole being the dominant Pole (IPD) typically employs frequency compensation techniques (e.g., miller compensation) to improve stability due to its large dc loop gain, which typically exhibits excellent power rejection ratio at low frequencies. However, when the operating frequency exceeds the frequency of its internal dominant pole, its PSR (Power Supply Rejection Ratio ) performance begins to deteriorate due to the rapid decrease in LDO loop gain. Eventually, the IPD-LDO gradually loses its ability to suppress power supply ripple at higher frequencies. To compensate for the lower PSR of the IPD-LDO at high frequencies, various FFRC (Feed-Forward Ripple Cancellation ) techniques have been developed, using additional active or passive networks to eliminate the power supply ripple. These techniques require accurate and complex power ripple feedforward mechanisms that are susceptible to variations in manufacturing processes and operating conditions. Compared to IPD-LDO, output-Pole-dominant (OPD) LDO has a better PSR over a wide frequency range. The output main pole is formed by a larger output capacitor, so that the LDO has lower output impedance after the working frequency is higher than the frequency of the output main pole, and the LDO can maintain good PSR even after the loop gain of the LDO in a medium-high frequency range is attenuated. In addition, after the working frequency exceeds the unit gain frequency, the filtering effect of the output capacitor can also ensure better high-frequency PSR. However, the stability of the feedback loop in an OPD-LDO depends on the output dominant pole frequency at low frequencies, and in order to guarantee loop stability, it is often necessary to use off-chip compensation capacitors of several microfarads. OPD-LDO may also employ on-chip compensation capacitors, but on-chip capacitors tend to have smaller capacitance values than off-chip capacitors, such that the output dominant pole moves to higher frequencies, resulting in reduced loop stability. One common solution to this problem is to incorporate a primary gate buffer, which is able to shift the non-main pole to a higher frequency, thereby ensuring adequate phase margin. Nevertheless, conventional gate buffer designs still require the use of relatively large on-chip capacitors due to limitations in increasing the frequency of non-dominant pole, resulting in a large silicon area. Disclosure of Invention In view of the above problems, the present invention provides an LDO circuit with a high power supply rejection ratio, which is based on an OPD-LDO with a FVF structure, a multistage buffer structure in series, and a ripple injection SRC technology, and has better PSR performance in a wide frequency band compared to LDOs with conventional structures. In order to solve the technical problems, the specific technical scheme of the invention is as follows: An LDO circuit with a high power supply rejection ratio comprises a reference module REF, an error amplifier module EA, a first buffer B1, a second buffer B2, a third buffer B3, a fourth buffer B4, a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6, a seventh MOS tube M7, a first power tube M P1, a second power tube M P2, a third power tube M P3, a fourth power tube M P4, a first resistor R 1, a second resistor R 2, a third resistor R F, a first capacitor C C, a second capacitor C F, a third capacitor C L, a first current source I B1 and a second current source I B2; The drain electrode of the first MOS tube M1 is connected with the grid electrode of the second MOS tube M2 and the input end of the first current source I B1, the grid electrode of the first MOS tube M1 is connected with the output end of the error amplifier module EA, the grid electrode of the sixth MOS tube M6 and one end of the first capacitor C C, and the source electrode of the first MOS tube M1 is connected with the output end V OUT of the LDO circuit, the drain electrode of the first power tube M P1, the drain electrode of the second power tube M P2, the drain electrode of the third power tube M P3, the drain electrode of the fourth power tube M P4, One end of the first resistor R 1 and one end of the third capacitor C L, the drain electrode of the second MOS tube M2 is grounded, the source electrode of the second MOS tube M2 is connected with the drain electrode